Semiconductor Memory Error Correction for Variable Retention Time
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Solution Overview
Problem
Existing nonvolatile semiconductor memory devices face inefficiencies in power consumption and circuit size due to the use of high-performance error correction mechanisms, which are wasteful when data retention time is short and result in unnecessary power usage and circuit scale expansion.
Innovation Solution
A semiconductor memory device with a dual error correction system, utilizing first and second error correction units with varying capabilities, where the first unit corrects errors with low power and small scale for short retention times, and the second unit with higher capability is used only when necessary for longer retention times, reducing overall power consumption and circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-performance error correction mechanism is used to guarantee correct information restoration after long retention, then error correction capability is improved, but power consumption increases and circuit scale expands
Solution Approach 1:
The patent applies dynamics by making the error correction mechanism adaptable rather than static. The control circuit dynamically selects between first and second error correction mechanisms based on the actual retention time of stored data. This allows the system to adjust its error correction capability to match the actual needs, avoiding unnecessary power consumption when high correction capability is not required.
Solution Approach 2:
The patent changes the parameter of error correction capability based on retention time. By measuring or estimating the retention time and comparing it against threshold values, the system switches between different error correction mechanisms with different correction capabilities. This parameter change allows the system to optimize power consumption while maintaining sufficient error correction capability.
2Reliability
If a high-performance error correction mechanism is used to guarantee correct information restoration after long retention, then error correction capability is improved, but circuit scale expands
Solution Approach 1:
The patent segments the error correction mechanism into two distinct parts: a first error correction mechanism with lower correction capability and smaller circuit scale, and a second error correction mechanism with higher correction capability and larger circuit scale. The control circuit selectively activates only the necessary segment based on retention time, thereby reducing the overall circuit scale while maintaining high error correction capability when needed.
Solution Approach 2:
The patent applies local quality by providing different error correction capabilities in different operational contexts. Instead of uniformly high error correction capability throughout, the system provides high correction capability only when retention time exceeds the second threshold, and lower correction capability when retention time is shorter. This localized approach reduces overall circuit complexity.
3Reliability
If error correction capability is increased to handle long retention times, then reliability is improved, but power consumption and circuit scale increase unnecessarily for short retention times
Solution Approach 1:
The patent applies partial action by providing only the necessary error correction capability required for the actual retention time. Instead of always using the full-capability second error correction mechanism, the system uses the first error correction mechanism (partial capability) when retention time is short, and only activates the second mechanism (full capability) when retention time exceeds the second threshold. This avoids excessive power consumption.
Solution Approach 2:
The control circuit dynamically adjusts the error correction capability based on real-time retention time assessment. This dynamic adaptation ensures that power is not wasted on excessive error correction capability when retention time is short, while still providing sufficient correction capability when retention time is long.
Data Source
AI summary
A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.