Memory Error Correction via On-Chip Serial Redundancy Programming
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Solution Overview
Problem
Existing memory error correction methods require human intervention and manual programming of redundancy information, which is inefficient and prone to errors, especially in electrical fuse-based systems where correcting erroneous memory cells involves complex mapping tables and parity bit associations.
Innovation Solution
The implementation of circuits within a chip that automatically convert error correction information from a parallel to a serial format and program redundancy information in a memory array, eliminating the need for manual intervention by automatically identifying and correcting erroneous memory cells using ECC parity bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If manual programming of redundancy information is used, then flexibility and adaptability are maintained, but productivity and time efficiency deteriorate due to human intervention requirements
Solution Approach 1:
The system performs self-correction by automatically detecting erroneous memory cells and programming redundancy information without external human intervention. The memory device itself executes the correction process through integrated circuits that identify errors and implement fixes using stored redundancy data.
Solution Approach 2:
Redundancy information including correct data and address mappings are pre-stored in the memory device before errors occur. When an error is detected, the system immediately uses the pre-prepared redundancy information to correct the error, eliminating the need for manual programming and significantly improving correction speed.
2Measurement precision
If mapping tables and parity bit associations are used, then error identification accuracy is improved, but device complexity increases due to additional lookup and programming steps
Solution Approach 1:
The patent combines the error detection, redundancy information storage, and correction execution functions into a single integrated system. The mapping tables and parity bit associations are merged with the memory structure itself, allowing the system to automatically translate error identifiers into correction actions without separate manual programming steps.
Solution Approach 2:
The patent introduces an intermediary circuit layer that automatically processes the relationship between parity bits, mapping tables, and redundancy information. This intermediary automatically translates error detection results into targeted redundancy programming actions, reducing the complexity visible to users while maintaining high accuracy.
3Productivity
If automatic correction circuits are implemented, then productivity and speed are improved, but device complexity increases due to additional circuits
Solution Approach 1:
The patent designs correction circuits that serve multiple functions: they detect errors, identify the specific erroneous cell using parity bits and mapping tables, retrieve the appropriate redundancy information, and execute the correction by programming the redundancy fuses. This multi-functionality reduces the need for separate dedicated circuits for each step, managing overall complexity while maintaining high correction speed.
Data Source
AI summary
A method includes, by a first circuit, converting a plurality of bits in a first format to a second format. The plurality of bits in the second format is used, by a second circuit, to program a plurality of memory cells corresponding to the plurality of bits. The first format is a parallel format. The second format is a serial format. The first circuit and the second circuit are electrically coupled together in a chip. In some embodiments, the plurality of bits includes address information, cell data information, and program information of a memory cell that has an error. In some embodiments, the plurality of bits includes word data information of a word and error code and correction information corresponding to the word data information of the word.