Memory Error Detection Circuit for Fast Single-Bit Code Checks
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Solution Overview
Problem
Conventional methods for detecting code errors in data accessed from memory devices require complex comparison circuits and increased time consumption as the number of bits in the error comparison code increases, leading to larger circuit sizes and higher component counts.
Innovation Solution
A method that sums each bit of the error comparison code to obtain a summation value, checking for carrying operations and equality to '1' to determine if the error comparison code matches a code error, thereby reducing detection time and circuit complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional pattern comparison method is used to detect code errors, then detection accuracy is maintained, but circuit complexity and component count increase with the number of bits in the error comparison code
Solution Approach 1:
The patent extracts the essential characteristic of code errors (single-bit errors represented by specific patterns like 0001, 0010, 0100, 1000) and creates a dedicated detection circuit that directly checks for these patterns using logic gates, rather than comparing against all possible error patterns. This extraction approach maintains detection accuracy while significantly reducing circuit complexity.
Solution Approach 2:
The patent uses a simplified logical copy of the error detection function instead of a full pattern comparison implementation. By copying only the essential detection logic (using AND, OR, NOT gates to check for specific error patterns), the circuit achieves the same detection capability with fewer components.
2Reliability
If conventional pattern comparison method is used to detect code errors, then comprehensive error detection is achieved, but time consumption increases
Solution Approach 1:
The patent performs preliminary action by pre-configuring the logic circuit with the specific error patterns it needs to detect (0001, 0010, 0100, 1000). The circuit is designed in advance to directly recognize these patterns through logical operations, eliminating the need for sequential comparison during actual error detection, thus reducing detection time while maintaining reliability.
3Reliability
If the number of bits in error comparison code increases, then detection coverage is improved, but the number of components required increases
Solution Approach 1:
The patent replaces the mechanical approach of increasing component count with each additional bit by using logical operations (AND, OR, NOT gates) that can handle variable bit lengths with the same basic component types. The logic circuit structure remains consistent regardless of the number of bits, as it uses systematic logical combinations to detect error patterns across any bit position.
Data Source
AI summary
A method for detecting a code error is proposed. The method is mainly applied for detecting whether there is a code error existed in the accessed data, in other words, for detecting whether there is only an error bit existed in the accessed data. After the data are accessed, the method generates an error comparison code correspondingly. Then, the method adds up each bit of the error comparison code to provide a summation value. After that, the method checks whether a carrying operation occurs and checks whether the summation value is equal to “1” when no carrying operation occurs. If no carrying operation occurs and the summation value is equal to “1”, the method determines that there is only an error bit existed in the accessed data. Thereby, the code errors are detected speedily and the number of the components for detection and the occupied area are reduced.