Memory Controller Error Modes for Snapshot Capture Without Host Interrupts

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Solution Overview

Problem

Conventional memory sub-systems inefficiently handle errors by interrupting the host system for every error occurrence, regardless of its severity, leading to wasteful slowdowns and inefficiencies.

Innovation Solution

A memory sub-system controller selectively determines if critical event trigger data corresponds to a fatal or non-fatal condition, performing different error handling modes accordingly, including partial or full snapshots, and managing debugging information storage to maintain system efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the memory sub-system interrupts the host system for every error occurrence, then error detection and handling reliability is improved, but system productivity and efficiency deteriorate due to wasteful slowdowns

Engineering Contradiction:
Improveerror detection and handling reliabilityVSAvoidsystem efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies local quality by differentiating error handling based on error severity. Fatal errors trigger host interrupts with full debugging information, while non-fatal errors are handled silently without host interruption. This selective approach ensures that only critical errors disrupt system operation, maintaining productivity while preserving reliability for serious issues.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter of error handling behavior based on error classification. By evaluating error severity and adjusting the response mode (interrupt vs. silent handling), the system optimizes between reliability and productivity dynamically. This parameter change allows the system to adapt its error handling strategy to match the actual threat level.

Inventive Principle:
Principle #35Parameter changes

2Loss of information

If the memory sub-system captures full snapshots for every error, then debugging information completeness is improved, but loss of time and computational resources worsen

Engineering Contradiction:
Improvedebugging information completenessVSAvoidsnapshot capture time
Core Design Contradiction:
Loss of informationVSLoss of time

Solution Approach 1:

The patent applies partial action by capturing only essential debugging information for non-fatal errors rather than complete system snapshots. For fatal errors, full snapshots are captured. This partial approach reduces time loss and resource consumption for less critical events while maintaining sufficient debugging capability when needed.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent segments debugging information capture into different levels: full snapshots for fatal errors and partial/essential information for non-fatal errors. This segmentation allows the system to allocate debugging resources proportionally to error severity, avoiding unnecessary time loss for minor issues while ensuring complete information capture for critical failures.

Inventive Principle:
Principle #1Segmentation

3Difficulty of detecting and measuring

If the memory sub-system stores comprehensive debugging information, then error analysis capability is improved, but device complexity and storage requirements worsen

Engineering Contradiction:
Improveerror analysis capabilityVSAvoiddebugging infrastructure complexity
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The patent applies local quality by storing different amounts of debugging information in different locations based on error type. Fatal errors trigger storage of comprehensive debugging data, while non-fatal errors store only essential information. This selective approach improves error analysis capability for critical issues without unnecessarily increasing device complexity and storage requirements for all error scenarios.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20260056669A1Selectable error handling modes in memory systems
Publication Date: 2026.02.26 MICRON TECHNOLOGY INC
  • US20260056669A1 patent drawing
  • US20260056669A1 patent drawing
  • US20260056669A1 patent drawing

AI summary

Aspects of the present disclosure configure a system component, such as memory sub-system controller, to capture debugging information in memory sub-system operations in response to a critical event. The memory sub-system controller receives critical event trigger data and determines whether the critical event trigger data corresponds to a fatal condition. The memory sub-system controller selects an error handling mode from a plurality of error handling modes based on determining whether the critical event trigger data corresponds to the fatal condition. A first of the plurality of error handling modes corresponds to storing a first set of debugging information associated with a memory sub-system. A second of the plurality of error handling modes corresponds to storing a second set of debugging information associated with the memory sub-system without interrupting a host. The second set can be a subset of the first set of debugging information.