Memory Error Detection Using Address-Dependent Split-Code Storage
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Solution Overview
Problem
Current methods for reading and writing data in memory systems are prone to errors, particularly accidental or deliberate errors during data writing, which can compromise the operation of electronic systems, and there is a need for more reliable and efficient error detection and correction mechanisms.
Innovation Solution
A method involving splitting a binary word representing data into two parts, with one part written in a first memory circuit and the other in a second circuit, using an error correcting or detecting code dependent on the data and address, allowing for error detection and correction by comparing internal control signals and recombining the parts to verify data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written in a single memory circuit, then the writing operation is simple and fast, but error detection capability is insufficient
Solution Approach 1:
The binary word is segmented into at least two parts, with each part being written to a separate memory circuit. This segmentation allows independent storage and comparison of data portions, enabling error detection through redundancy while maintaining manageable circuit complexity
Solution Approach 2:
The patent creates redundant copies of data parts across multiple memory circuits. By writing the same or related data portions to multiple circuits and comparing internal control signals, the system detects errors without requiring completely new circuit architectures
2Reliability
If error correcting code is added to each binary word, then error detection capability improves, but storage space and writing complexity increase
Solution Approach 1:
The patent merges the error detection function with the existing memory structure by utilizing internal control signals that are already present during writing operations. Instead of adding separate error detection circuits or redundant storage for correction codes, the system repurposes existing control mechanisms for dual purposes: normal operation and error detection
Solution Approach 2:
The memory system performs self-diagnosis by comparing internal control signals across multiple circuits during normal writing operations. The system uses its own operational signals to detect errors without requiring external verification mechanisms or additional storage dedicated solely to error detection
3Measurement precision
If multiple memory circuits are used with signal comparison, then error detection accuracy improves, but operation time and system complexity increase
Solution Approach 1:
The error detection process occurs continuously during normal writing operations rather than as a separate post-processing step. By comparing internal control signals in real-time as data is being written, the system achieves accurate error detection without adding significant operation time
Solution Approach 2:
The patent performs error detection during the writing operation itself, before data is fully committed to storage. By comparing control signals while the writing process is ongoing, the system identifies errors early in the operation sequence, preventing corrupted data from being finalized
Data Source
AI summary
A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.