3D Memory Source-Layer Etch Stops for Stable Leakage Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high operational reliability and large capacity while maintaining portability, particularly in three-dimensional designs where dopant diffusion and process errors in junction overlap regions can lead to unstable gate-induced drain leakage currents during erase operations.
Innovation Solution
The semiconductor memory device incorporates a stack structure with etch stop layers and a source layer, where the etch stop layers are made of insulating materials like SiCO and SiCN, limiting dopant diffusion to the surface contact between the channel and source layers, thereby reducing process errors and ensuring stable gate-induced drain leakage currents. This design includes a channel structure penetrating the etch stop layers and a source layer, with interposition parts and memory layers, and a manufacturing method that forms these layers sequentially to enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dopant diffusion is allowed in the source layer during manufacturing, then the source layer can be formed effectively, but process errors occur in junction overlap regions leading to unstable gate-induced drain leakage currents
Solution Approach 1:
An etch stop layer is introduced as an intermediary component between the source layer and the channel structure. This etch stop layer acts as a mediator that prevents dopant diffusion into the channel region while still allowing the source layer to be formed. The etch stop layer has specific etch selectivity that enables precise control during manufacturing processes, thereby eliminating process errors in junction overlap regions and stabilizing gate-induced drain leakage currents without compromising source layer formation.
2Manufacturing precision
If the etch stop layer material has high etch selectivity with respect to the source layer, then manufacturing precision is improved, but device complexity increases due to additional material layers
Solution Approach 1:
The patent utilizes parameter changes in material composition to achieve high etch selectivity. By carefully selecting the chemical composition of the etch stop layer (such as using silicon oxide, silicon nitride, or silicon oxynitride) and adjusting its thickness parameters, the patent achieves precise control over etching processes. This allows the etch stop layer to be selectively removed or retained during manufacturing steps without requiring excessive additional layers, thereby maintaining manufacturing precision while controlling device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves operational reliability by reducing dopant diffusion distance and process errors, ensuring stable gate-induced drain leakage currents and enhancing the reliability of semiconductor memory devices, particularly in three-dimensional configurations.
Implementation Method 1
a material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.