3D Memory Channel Hole Etching With Contact Protection Walls

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Solution Overview

Problem

Existing 3D memory device fabrication methods require separate processes for forming dummy channel holes in the contact area, leading to increased fabrication costs and complexity, particularly during gate line slit etching and removal of dielectric layers.

Innovation Solution

A method involving the formation of a protection region in the contact area with protection layers that surround the contact region, using a material resistant to etching, allowing simultaneous etching of first and second channel holes, and reducing the need for additional processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If separate processes are used for forming dummy channel holes in the contact area, then the fabrication process can be completed, but the fabrication cost and complexity increase

Engineering Contradiction:
Improvefabrication process simplicityVSAvoidfabrication process complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent merges the formation of dummy channel holes in the contact area with the formation of real channel holes in the core area by using a unified etching process. The protection wall is integrated into the existing fabrication flow, allowing both types of holes to be created simultaneously rather than through separate sequential steps, thereby reducing overall process complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The protection wall acts as an intermediary structure that enables the unified etching process. This protective layer allows the etching process to proceed uniformly across both contact and core areas while preventing unwanted etching in the contact region, serving as a mediator that reconciles the need for different hole types in different regions

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If separate processes are used for gate line slit etching and dielectric layer removal, then complete fabrication is achieved, but fabrication cost increases

Engineering Contradiction:
Improvefabrication completenessVSAvoidnumber of fabrication steps
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent combines multiple fabrication steps into a unified process flow. The protection wall structure enables simultaneous handling of gate line slit etching and dielectric layer removal operations, reducing the total number of separate processes required while ensuring complete fabrication of all necessary structures

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If dummy channel holes are formed separately, then contact area structures are complete, but etching precision decreases

Engineering Contradiction:
Improvestructural completenessVSAvoidetching precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The protection wall implements local quality by providing differentiated protection in different regions. It creates a localized protective barrier in the contact area while allowing the etching process to proceed normally in the core area, ensuring each region receives the appropriate treatment for its specific structural requirements and maintaining high etching precision throughout

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the fabrication process by integrating dummy channel holes with core area channels, reduces fabrication costs, and enhances etching precision, ensuring uniform dimensions and minimizing interference between core and contact areas.

Implementation Method 1

substituting portions of the plurality of second dielectric layers that surround the plurality of first channel holes with a protection material to form a protection wall

Methodology Applied
Scientific EffectEtching resistance:

Data Source

PatentUS12432923B2Memory device and fabrication method thereof
Publication Date: 2025.09.30 YANGTZE MEMORY TECH CO LTD
  • US12432923B2 patent drawing
  • US12432923B2 patent drawing
  • US12432923B2 patent drawing

AI summary

A memory device fabrication method includes providing a semiconductor structure having a core area and a contact area arranged next to each other along a first direction. The semiconductor structure includes dielectric layer pairs that include first and second dielectric layers stacked in an alternating manner in a second direction approximately perpendicular to the first direction. The method further includes performing etching to form channel holes penetrating the dielectric layer pairs. The channel holes include first channel holes in the contact area and second channel holes in the core area. The first channel holes surround a contact region. The method also includes substituting portions of the second dielectric layers that surround the plurality of first channel holes with a protection material to form a protection wall that surrounds the contact region.