Memory Evaluating Board Single PCIe Edge Bifurcation

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Solution Overview

Problem

Evaluating SSDs with dual ports requires connecting SSDs to SSD evaluating boards using two PCIe card edges and two PCIe card slots, which can degrade communication quality due to the use of extension cables, especially when the PCIe card edges are connected to PCIe card slots adjacent to each other.

Innovation Solution

A memory evaluating board with a single PCIe card edge that utilizes PCIe bifurcation to enable communication between the SSD and the evaluating apparatus, allowing for the evaluation of both single and dual port SSDs without the need for multiple PCIe card edges, thereby improving communication quality by switching lane connections between link controllers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If two PCIE card edges are connected to two PCIE card slots using extension cables to evaluate dual port SSD, then the SSD can be connected to the evaluating board, but the communication quality between the SSD and the PC degrades

Engineering Contradiction:
Improveconnectability of dual port SSDVSAvoidcommunication quality
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent merges the functionality of two PCIE card edges into a single PCIE card edge by implementing a switch that can dynamically allocate lanes to simulate either a single port or dual port configuration. This eliminates the need for extension cables and multiple card slots while maintaining the ability to evaluate both single port and dual port SSDs, thereby preserving communication quality.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a dynamic lane allocation mechanism through a switch that can reconfigure the connection between lanes and link controllers based on the SSD type being evaluated. This dynamic reconfiguration allows a single card edge to adaptively serve both single port and dual port SSDs without requiring physical reconnection or extension cables, thus maintaining stable communication.

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If multiple PCIE card edges are used to evaluate dual port SSD, then the dual port functionality can be supported, but the hardware complexity and requirements increase

Engineering Contradiction:
Improvesupport for dual port SSDVSAvoidnumber of PCIE card edges and slots
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal PCIE card edge design that can evaluate both single port and dual port SSDs through a single interface. The switch-based lane allocation system provides multi-functionality, allowing the same hardware configuration to adapt to different SSD types, thereby eliminating the need for separate card edges and slots for different evaluation scenarios.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent segments the PCIE lanes into separate groups that can be independently allocated to different link controllers through a switch. This segmentation allows flexible configuration where lanes can be grouped to support either single port or dual port operations, reducing the need for multiple physical card edges while maintaining the capability to evaluate different SSD configurations.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240345973A1Memory evaluating board and memory evaluating method
Publication Date: 2024.10.17 KIOXIA CORP
  • US20240345973A1 patent drawing
  • US20240345973A1 patent drawing
  • US20240345973A1 patent drawing

AI summary

In one embodiment, a memory evaluating board includes a first portion configured to mount a first memory including first and second lanes thereto, a second portion including an edge configured to connect to a slot of an apparatus that includes a first controller including first and second lanes and a second controller including first and second lanes, and a communication controller mounted to the first portion, and configured to control communication between the first memory and the apparatus. In case where the first memory is a single port, the communication is performed between the first and second lanes of the first memory and the first and second lanes of the first controller, respectively. In case where the first memory is a dual port, the communication is performed between the first and second lanes of the first memory and the first lanes of the first and second controllers, respectively.