Memory Device Evaluation-Time Control for Threshold Distributions
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Solution Overview
Problem
Existing memory devices face challenges in maintaining a narrow threshold voltage distribution due to varying program speeds of memory cells, leading to widened distributions and inefficiencies in verify operations.
Innovation Solution
A memory device with a control logic system that adjusts evaluation times in multiple program loops to reduce the difference between first and second evaluation times during double verify operations, improving threshold voltage distribution by differentiating between slow and fast cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single verify voltage is used for verifying memory cells, then the verify operation is simple, but the threshold voltage distribution width is widened due to different program speeds of memory cells
Solution Approach 1:
The verify operation is segmented into multiple verify operations with different verify voltages. The memory cells are verified multiple times using progressively adjusted verify voltages (e.g., first verify voltage, second verify voltage higher than the first) to account for different program speeds. This segmentation allows fast cells and slow cells to be verified at appropriate voltage levels, preventing threshold voltage distribution widening while maintaining manageable complexity through systematic voltage adjustment.
Solution Approach 2:
The verify voltage is made dynamic rather than fixed. The verify voltage is adjusted based on the program loop iteration and the specific memory cell's program speed characteristics. Fast cells are verified with lower verify voltages earlier in the program process, while slow cells receive higher verify voltages in later iterations. This dynamic voltage adjustment ensures narrow threshold voltage distribution without requiring overly complex static verification schemes.
2Ease of operation
If the same program voltage is applied to all memory cells, then the program operation is simple, but the threshold voltage change amount varies significantly between fast cells and slow cells
Solution Approach 1:
The program operation uses periodic program loops with repeated program-verify cycles. Instead of applying a single program voltage once, the system performs multiple program loops where program voltages are applied periodically with verify operations in between. This periodic action allows the system to monitor and adjust for different program speeds of fast and slow cells, achieving consistent threshold voltage changes across all cells while maintaining relatively simple operation through standardized loop structures.
Solution Approach 2:
The program voltage parameter is changed across different program loops and iterations. Rather than using a fixed program voltage, the system adjusts program voltage levels based on the program progress and cell response. Fast cells receive appropriate program voltage levels that prevent over-programming, while slow cells receive adjusted voltage levels to ensure sufficient programming. This parameter change strategy achieves consistent threshold voltage distribution without requiring completely complex adaptive control.
3Measurement precision
If evaluation time difference between first and second verify operations is large, then the verify operations can be performed with sufficient accuracy, but the program operation time increases
Solution Approach 1:
The evaluation time is made dynamic and adaptive rather than using fixed, conservative time values. The system adjusts evaluation time based on the program loop iteration, verify voltage level, and detected cell program speed characteristics. In early program loops with fast cells, shorter evaluation times are used. In later loops with slow cells, evaluation times are extended as needed. This dynamic timing maintains verify operation accuracy while minimizing overall program operation time by avoiding unnecessarily long evaluation periods.
Solution Approach 2:
The verify operations provide feedback about cell program status and speed, which is used to adjust subsequent evaluation times. The system monitors the results of each verify operation and uses this feedback to optimize the duration of subsequent evaluation periods. If cells are programming quickly, the system reduces evaluation time. If cells are slow to program, the system extends evaluation time only when necessary. This feedback-driven approach maintains measurement precision while significantly reducing wasted time in the program operation.
Data Source
AI summary
A memory device includes a plurality of memory cells programmed to a first program state through a plurality of program loops, a page buffer configured to perform a verify operation of verifying the first program state in each of the plurality of program loops, and control logic configured to, as the plurality of program loops are sequentially performed, adjust a first evaluation time of a first evaluation operation so as to decrease the difference between a second evaluation time of a second evaluation operation and the first evaluation time.