Memory Block Program Exit Pulses for Unselected Leakage Mitigation
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Solution Overview
Problem
Unselected blocks in memory devices experience leakage due to ineffective cutoff by select gate devices, leading to increased error rates during read operations, particularly after program operations, which affects the reliability and performance of memory sub-systems.
Innovation Solution
Implementing a program exit phase with high voltage pulses on bitlines and select gate devices to counteract charge leakage, maintaining a higher channel potential and reducing leakage effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If select gate devices are used to cutoff unselected blocks, then block isolation is achieved, but charge leakage occurs leading to increased error rates
Solution Approach 1:
The patent applies preliminary anti-action by introducing a program exit phase that actively counteracts charge leakage before it can significantly impact read operations. High voltage pulses are applied to bitlines and select gate devices during this phase to prevent charge accumulation in unselected blocks, thereby mitigating the harmful leakage effect before it degrades read accuracy
Solution Approach 2:
The patent changes operational parameters by introducing a dedicated program exit phase with specific voltage conditions. During this phase, bitlines are maintained at high voltage levels and select gate devices receive specific control signals, creating a temporary parameter state that actively suppresses charge leakage without requiring structural modifications to the select gate devices
2Quantity of substance
If program operations are performed on selected blocks, then data storage is achieved, but charge leakage to unselected blocks increases
Solution Approach 1:
The patent applies preliminary action by implementing a program exit phase immediately following program operations. This phase prepares the memory device by applying high voltage pulses to bitlines and specific control signals to select gate devices before read operations commence, thereby preemptively reducing charge leakage to unselected blocks and ensuring data integrity
Solution Approach 2:
The patent introduces an intermediary control mechanism through the program exit phase. The control circuit acts as an intermediary that coordinates voltage application to bitlines and control signals to select gate devices, creating a mediating effect that suppresses charge leakage during the transition from program to read operations without interfering with the primary data storage function
3Object-generated harmful factors
If high voltage pulses are applied to bitlines and select gate devices, then charge leakage is reduced, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the control circuit to perform multiple functions: it manages normal read/write operations, implements the program exit phase with high voltage pulse generation, and coordinates select gate device control signals. This multi-functionality reduces the need for separate dedicated circuits for leakage mitigation, thereby limiting the increase in overall device complexity while achieving charge leakage reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Mitigates unselected block leakage, improving read operation performance and reducing error rates without altering the select gate device structure, enhancing the overall quality of service for host systems.
Implementation Method 1
application of the positive voltage pulse creates a potential difference between the bitline and the negative channel potential, which pulls the channel potential up to a higher, non-negative, level
Data Source
AI summary
A memory device includes a memory array with a plurality of memory cells formed at respective intersections of a plurality of wordlines and a plurality of bit lines. The memory device further control logic to initiate a program operation on one or more memory cells in a first block of the memory array, the program operation comprising a program phase, a program recovery phase, and a program exit phase. The control logic further causes a positive voltage pulse having a fixed duration to be applied to at least a subset of a plurality of bitlines of the memory array during the program exit phase of the program operation and causes the positive voltage pulse having the fixed duration to be applied to an access line controlling one or more drain-side select gate devices in the first block of the memory array during the program exit phase of the program operation.