Memory Expander Microchip for Processor Memory Compression
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Solution Overview
Problem
Systems with directly attached processor memory face limitations in memory bandwidth and lack of compression logic, making it difficult to efficiently implement memory compression, especially for processors like the industry standard x86 that do not support memory compression.
Innovation Solution
A memory expander microchip is introduced, which provides additional bandwidth and logic to enable memory compression by storing frequently used data in directly attached memory and less frequently used data in a secondary memory, using a compression/decompression engine and data caching to manage memory operations without burdening the processor or operating system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory compression is implemented in a system with directly attached processor memory, then memory capacity is expanded, but memory bandwidth requirement increases beyond what is available
Solution Approach 1:
The patent divides the memory system into two separate memory controllers: one for uncompressed memory and one for compressed memory. This segmentation allows each controller to be optimized for its specific function, with the compressed memory controller having dedicated compression logic and bandwidth resources, thereby resolving the bandwidth bottleneck that would occur if compression were implemented in the single attached memory system.
Solution Approach 2:
The patent introduces a compressed memory controller as an intermediary component between the processor and the compressed memory. This intermediary handles all compression/decompression operations and memory management tasks, offloading the processor and providing dedicated bandwidth for compressed memory operations without interfering with the directly attached uncompressed memory operations.
2Quantity of substance
If memory compression logic is added to enable memory compression, then memory capacity is increased, but device complexity increases
Solution Approach 1:
The patent extracts the compression logic from the processor and places it in a separate compressed memory controller. This extraction allows the processor to remain simple and focused on computation, while the compression functionality is isolated in a dedicated component that can be added to the memory subsystem without increasing processor complexity.
Solution Approach 2:
The compressed memory controller serves multiple functions: it manages compressed memory allocations, performs compression/decompression operations, handles memory mapping, and interfaces with both the processor and compressed memory. This multi-functionality consolidates what would otherwise be separate components, reducing overall system complexity despite adding compression capability.
3Quantity of substance
If more physical memory is added to maintain the memory-to-processor ratio, then memory capacity increases, but system cost and physical resources increase
Solution Approach 1:
The patent changes the state of stored data from uncompressed to compressed form, thereby changing the effective capacity parameter of the existing physical memory. By compressing data in the second memory, the system achieves higher effective storage capacity from the same physical memory resources, avoiding the need to add more physical memory modules.
4Device complexity
If compression operations are performed without dedicated logic, then device complexity is reduced, but processing overhead increases
Solution Approach 1:
The patent implements preliminary action by having the compressed memory controller proactively manage compression operations, including pre-compressing data before it needs to be accessed and pre-allocating memory resources. This preliminary management reduces the need for time-critical compression operations during active processing, thereby reducing processing overhead despite having dedicated compression logic.
Data Source
AI summary
A method, apparatus and program product enable memory compression for a system including processor with directly attached memory. A memory expander microchip facilitates memory compression while attached to a processor. The memory expander microchip may provide additional bandwidth and memory capacity for the system to enable memory compression in a manner that does not burden the attached processor or associated operating system. The processor may store uncompressed data in its lower latency, directly attached memory, while the memory attached to the memory expander may store either or both compressed and uncompressed data.