Memory Fabric Clock Bypass for Low-Latency Stutter Mode
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Solution Overview
Problem
The increasing complexity and power consumption of computing systems with multiple components on a single chip or multi-chip modules pose challenges in power management, particularly in transitioning between operating modes, which affects efficiency and battery life in mobile devices.
Innovation Solution
The implementation of a dynamic clock control system that partitions the communication fabric into stutter and non-stutter regions, using a bypass clock during stutter mode to reduce power consumption by powering down the phase-locked loop (PLL) and utilizing a low-power bypass clock to service predictable, periodic clients while maintaining non-stutter regions in a power-gated state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the PLL is powered down during stutter mode to reduce power consumption, then power consumption is reduced, but exit latency increases due to the time required to power up and lock the PLL
Solution Approach 1:
The bypass clock is kept running continuously in advance, so when stutter mode is exited, the clock is already available immediately without requiring PLL power-up and locking. This preliminary preparation of the clock eliminates the exit latency penalty while still allowing the PLL to be powered down during stutter mode for power savings.
2Loss of energy
If the fabric is partitioned into stutter and non-stutter regions with selective power-gating, then power consumption is reduced during idle periods, but device complexity increases due to the need for region partitioning and clock management
Solution Approach 1:
The fabric is divided into stutter regions and non-stutter regions that can be independently power-gated. This segmentation allows selective power management where only the necessary regions remain active, reducing overall power consumption while maintaining functional integrity of the fabric.
Solution Approach 2:
The bypass clock serves multiple functions: it clocks the stutter region during active mode, provides the clock during stutter mode when PLL is powered down, and enables fast exit from stutter mode. This multi-functionality reduces the need for separate clock management mechanisms for different regions.
3Adaptability or versatility
If multiple components are integrated on a single chip to increase functionality, then adaptability is improved, but power consumption increases due to the complexity of interconnecting components
Solution Approach 1:
The fabric components are segmented into stutter and non-stutter regions that can be independently power-managed. This allows the system to maintain high functionality by keeping necessary components integrated on-chip while reducing power consumption by power-gating inactive regions during low-activity periods.
Data Source
AI summary
Systems, apparatuses, and methods for implementing dynamic clock control to increase stutter efficiency in a memory subsystem are disclosed. A system includes at least a processor, a memory, and a communication fabric coupled to the processor and memory. The system implements a stutter mode for a first region of the fabric, with stutter mode including an idle state and an active state. Stutter efficiency is defined as the idle time divided by the sum of the active time and the idle time. Reducing the exit latency of going from the idle state to the active state increases the stutter efficiency which increases the power savings achieved by implementing the stutter mode. Since the phase-locked loop (PLL) is one of the main contributors to the exit latency, the PLL is powered down and one or more bypass clocks are provided during the stutter mode.