Semiconductor Memory Fail Address Storage in Array Region
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Solution Overview
Problem
As semiconductor memory devices become more integrated and faster, the ratio of failed cells that do not operate correctly increases, necessitating an efficient method to repair these cells to improve yield and performance.
Innovation Solution
A method and system for a semiconductor memory device that includes a memory cell array, a test/repair manage circuit, and a control logic circuit, where memory cells in a first region are tested to detect failed cells, and the fail addresses are stored in a second region of the memory cell array, allowing for repair operations after packaging, without requiring extra memory for fail addresses and reducing occupied area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are tested and fail addresses are stored in an external memory, then failed cells can be repaired, but the device requires extra memory space and has increased complexity
Solution Approach 1:
The patent combines the fail address storage function with the existing memory cell array by designating a second region within the array for storing fail addresses. This merging eliminates the need for separate external memory structures and reduces overall device complexity while maintaining the capability to repair failed cells.
Solution Approach 2:
The memory cell array is designed to serve multiple functions: storing normal data in the first region and storing fail addresses in the second region. This multi-functionality reduces the need for dedicated separate structures and simplifies the overall device architecture.
2Reliability
If fail addresses are stored in a separate external memory, then failed cells can be identified and repaired, but the occupied area increases
Solution Approach 1:
The patent merges the fail address storage function into the existing memory cell array structure by allocating a second region within the array. This eliminates the need for separate external memory and reduces the total occupied area while maintaining full repair capability.
Solution Approach 2:
The patent organizes the memory array into distinct regions (first region for normal data, second region for fail addresses) within the same physical space. This spatial organization allows multiple functions to coexist without increasing the overall footprint of the device.
3Productivity
If more memory cells are integrated to increase capacity, then device performance improves, but the ratio of failed cells increases
Solution Approach 1:
The patent implements a preliminary testing phase before normal operation where memory cells are tested and fail addresses are identified and stored in the second region. This preliminary action allows the device to proactively identify and prepare for repairs, enabling subsequent repair operations that restore reliability after integration scaling.
Solution Approach 2:
The testing mechanism provides feedback about failed cells, allowing the system to identify and repair defects. This feedback loop enables continuous improvement of reliability even as integration density increases.
Data Source
AI summary
A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which includes a plurality of bank arrays, memory cells in a first region of the memory cell array are tested to detect one or more failed cells in the first region, a fail address corresponding to the detected one or more failed cells is determined and the determined fail address is stored in a second region different from the first region, in the memory cell array.