Semiconductor Memory Fail Detection Circuit
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Solution Overview
Problem
As semiconductor memory devices become more highly integrated, the increased number of memory cells leads to a higher likelihood of failed cells, necessitating efficient testing and repair methods to replace defective cells without significantly increasing testing time and cost.
Innovation Solution
A semiconductor memory device with a fail detection circuit that compares read data with test data to generate comparison signals, accumulates and stores fail information, and outputs it to facilitate repair operations, using a fail bit indicator and comparison circuit to efficiently identify and replace failed memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to improve memory capacity, then the memory capacity increases, but the number of failed memory cells increases
Solution Approach 1:
The memory cell array is divided into multiple blocks, and fail information is accumulated and stored for each block separately. This segmentation allows targeted repair of failed cells within specific blocks while maintaining functionality of other blocks, thus handling increased memory capacity with improved reliability management.
2Reliability
If traditional testing methods are used to identify failed memory cells, then failed cells can be detected, but testing time and cost increase significantly
Solution Approach 1:
Fail information is accumulated and stored during the manufacturing process before the device is fully assembled and shipped. By performing fail detection and information storage in advance, the need for extensive post-assembly testing is reduced, significantly decreasing testing time and cost while maintaining reliable detection of failed cells.
Solution Approach 2:
The memory device includes built-in fail detection circuits and accumulators that automatically detect and record fail information during manufacturing without requiring external testing equipment. This self-service capability eliminates the need for time-consuming external testing processes.
3Ease of repair
If redundant memory cells are added to replace failed cells, then repair capability is improved, but device complexity increases
Solution Approach 1:
Redundant memory cells are organized in a structured manner with specific replacement relationships defined for different blocks. The fail information storage structure maintains local mapping between failed cells and their replacements, allowing targeted repair operations that minimize the impact on overall device complexity while maintaining strong repair capability.
Data Source
AI summary
A semiconductor memory device includes a memory core and a fail detection circuit. The memory core includes a memory cell array having a plurality of memory cells. The fail detection circuit compares read data with test data to generate a comparison signal representing whether each of the memory cells is failed or not, and accumulates and stores fail information of the memory cells corresponding to a plurality of addresses to output accumulated fail information. The read data are read out from the memory cells in which the test data are written.