Selective Post-Package Repair for Memory Chip Fail Rows

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Solution Overview

Problem

Volatile memory devices with defective memory cells are treated as defective products due to space limitations for storing fail addresses, limiting the number of redundancy memory cells available for repair.

Innovation Solution

A memory device performs selective post package repair by storing fail addresses based on the number of defective memory cells connected to word lines or bit lines, using redundancy memory cells to replace defective ones.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the volatile memory device includes redundancy memory cells to replace defective memory cells, then the production yield is improved, but the space for storing fail addresses is limited

Engineering Contradiction:

Improveproduction yieldVSAvoidspace for storing fail addresses

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent segments the address storage function by dividing fail addresses into multiple groups based on the number of defective memory cells. Different groups of fail addresses are stored in different locations or with different storage capacities, allowing the system to handle varying numbers of defects without requiring a single large storage space for all possible fail addresses.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements partial repair action by selectively replacing only certain defective memory cells with redundancy memory cells based on the number of defects detected. Instead of attempting to store and repair all possible fail addresses, the system performs repair actions on a subset of defective cells, which is sufficient to maintain production yield while conserving storage space.

Inventive Principle:

Principle #16Partial or excessive action

2Reliability

If the number of redundancy memory cells is increased to replace more defective memory cells, then more defective cells can be repaired, but the device space is limited

Engineering Contradiction:

Improverepair capabilityVSAvoiddevice space

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent implements dynamic allocation of redundancy memory cells based on the actual number and distribution of defective memory cells detected during testing. The system adjusts which redundancy cells are activated and how fail addresses are stored, optimizing the use of limited device space while maintaining the necessary repair capability for the specific defect pattern encountered.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS12474993B2Memory devices performing selective post package repair, electronic devices including the same, and operating methods of the same

Publication Date: 2025.11.18 SAMSUNG ELECTRONICS CO LTD

AI summary

Disclosed is a memory device which includes a plurality of memory chips. Each of the plurality of memory chips, in response to a post package repair (PPR) command and a target value received from a controller, performs a write operation of write data with respect to memory cells corresponding to a row address generated in a PPR mode executed in response to the PPR command, performs read operation with respect to the memory cells, resulting in read data, generates a comparison signal based on a result of comparing the write data and the read data programs the row address corresponding to the comparison signal as a selected fail row address, and writes the write data in redundancy memory cells, which are connected to a redundancy word line used to replace a fail word line corresponding to the selected fail row address, from among the plurality of memory cells.