Semiconductor Memory Device Fail-Search Logic Circuit
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Solution Overview
Problem
Conventional NAND flash memory devices face challenges in data write speed due to the time-consuming binary search method used to identify failed columns, which occupies column address circuits and prevents external address input during the verification process.
Innovation Solution
A semiconductor memory device configuration that includes a fail-search chain with series-connected logical gates and a reset instruction unit, allowing for immediate detection and specification of failed columns without requiring column addresses, enabling simultaneous external address input during detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If binary search is employed to specify a failed column, then the verification result can be determined, but time is taken and data write speed is lowered
Solution Approach 1:
The column address circuit is segmented into multiple functional parts: a first part that activates half of the columns based on initial verification results, and a second part that activates the remaining half. This segmentation allows parallel processing of column verification, reducing the time needed to identify failed columns compared to sequential binary search.
Solution Approach 2:
The circuit performs preliminary activation of column addresses in parallel before final verification. By pre-activating half of the columns and then half of the remaining columns, the system prepares the verification structure in advance, enabling faster determination of failed columns without requiring time-consuming sequential search.
2Measurement precision
If binary search is employed to specify a failed column, then the verification process can complete, but the column address circuit is occupied and external address input cannot be accepted
Solution Approach 1:
The column address circuit is designed with dynamic activation characteristics. The first part activates half of the columns, and the second part activates the remaining half, allowing the circuit to adaptively respond to both internal verification needs and external address input requirements. This dynamic design enables the circuit to switch between verification mode and address input mode flexibly.
Solution Approach 2:
By dividing the column address circuit into first and second parts that handle different portions of column activation, the system creates independent functional blocks. This segmentation allows one part to be occupied by verification while the other can simultaneously handle external address input, maintaining adaptability during the verification process.
3Measurement precision
If binary search is employed, then failed column can be identified, but data write speed is lowered due to time consumption
Solution Approach 1:
The verification process continues without interruption by using parallel column activation. The first part activates half of the columns while the second part activates the remaining half, ensuring that verification actions are performed continuously and in parallel rather than sequentially. This maintains useful action continuity and improves data write speed.
Solution Approach 2:
The circuit performs preliminary parallel activation of column addresses before final verification completion. By pre-activating half of the columns and then half of the remaining columns in a structured sequence, the system prepares verification structures in advance, enabling faster overall verification and improving data write speed without sacrificing identification accuracy.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes memory cells, holding circuits, and a logical gate chain. The memory cells are associated with columns. The holding circuits are associated with the columns and capable of holding first information indicating whether associated one of the columns is a verify-failed column or not. The logical gate chain includes a plurality of first logical gates associated with the columns and connected in series. Each of the first logical gates outputs a logical level to a next-stage first logical gate in a series connection. The logical level indicates whether the verify-failed column exists or not based on the first information in associated one of the holding circuit. The content indicated by the logical level output from each of the first logical gates is inverted using one of the first logical gates associated with the verify-failed column as a border.