Memory Fail Signal Line for Poll-Free Program Failure Detection

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Solution Overview

Problem

Memory devices often experience write/program failures due to worn-out or defective memory cells, which can lead to operational inefficiencies and the need for polling status registers, tying up the memory bus and slowing down operations.

Innovation Solution

Implementing an asynchronous electronic fail signal to indicate program failures, allowing the controller or processor to manage failures without polling, thereby improving memory speed by avoiding bus tie-ups and enabling faster operations as the number of parallel NVM devices increases.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If polling status registers is used for error detection, then program failures can be detected, but the memory bus is tied up and operation speed decreases

Engineering Contradiction:

Improveprogram failure detectionVSAvoidmemory operation speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent extracts the failure detection function from the polling process by implementing a dedicated fail signal line that independently indicates program failures. This separates the error detection mechanism from the main data bus operations, allowing failure detection without tying up the memory bus for polling status registers.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary fail signal line that acts as a dedicated communication channel between the memory device and controller for error indication. This intermediary mechanism enables reliable failure detection while avoiding the bottleneck of using the main data bus for status polling.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If polling status registers is used for error detection, then program failures can be detected, but operation efficiency decreases due to bus tie-ups

Engineering Contradiction:

Improveprogram failure detectionVSAvoidmemory operation efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent enables continuous memory operations by maintaining the data bus available for productive work while the fail signal line continuously monitors and reports errors independently. This ensures that error detection does not interrupt or slow down the main data processing operations.

Inventive Principle:

Principle #20Continuity of useful action

3Quantity of substance

If multiple parallel non-volatile memory devices are used, then storage capacity increases, but the complexity of managing failures across devices increases

Engineering Contradiction:

Improvestorage capacityVSAvoidfailure management complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent merges the failure indication functions of multiple parallel memory devices onto a single shared fail signal line. This consolidation allows the controller to monitor all devices for errors through one unified interface, significantly simplifying failure management while maintaining support for multiple high-capacity devices.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20110271165A1Signal line to indicate program-fail in memory

Publication Date: 2011.11.03 MICRON TECHNOLOGY INC

AI summary

Subject matter disclosed herein relates to a memory device and a method of operating same.