Memory Cell Fail-Bit Detection for Retention-Aware Operation
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Solution Overview
Problem
Memory devices experience reliability issues due to retention, which causes deterioration of memory cells, affecting read, program, and erase operations, necessitating improved reliability through optimization based on deterioration degrees.
Innovation Solution
A memory device with a peripheral circuit and control logic performs a fail bit detection operation to measure the deterioration of memory cells, setting target parameters for operations like read, program, and erase based on comparison with reference times, optimizing operations accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory operations are performed using fixed parameters, then the operation process is simple, but the reliability decreases due to memory cell deterioration from retention
Solution Approach 1:
The patent performs a fail bit detection operation before the main memory operation to measure the deterioration degree of memory cells in advance. Based on this preliminary measurement, target parameters for the main operation are determined, allowing the system to adapt to memory cell deterioration without complicating the main operation process.
Solution Approach 2:
The patent changes operation parameters (such as read voltage, program voltage, erase voltage) based on the deterioration degree of memory cells. By adjusting these parameters according to the measured fail bit detection time, the system maintains high reliability despite memory cell degradation over time.
2Measurement precision
If memory operations are performed without considering deterioration degree, then the operation process is simple, but the accuracy of operation results decreases
Solution Approach 1:
The patent uses the fail bit detection time as feedback to determine appropriate target parameters for main operations. The control logic adjusts parameters based on this feedback, ensuring accurate operation results while keeping the parameter setting process automated and manageable.
Solution Approach 2:
The patent replaces manual or complex parameter adjustment mechanisms with an automated control logic system that determines parameters based on fail bit detection results. This substitution maintains measurement precision while reducing the complexity of parameter setting.
3Reliability
If fail bit detection operation is performed to measure deterioration, then the reliability improves, but the operation time increases
Solution Approach 1:
The patent performs a simplified fail bit detection operation that measures only the essential deterioration indicator (time until fail bit detection) without conducting a full comprehensive test. This partial action approach maintains reliability improvement while minimizing the time penalty.
Solution Approach 2:
The fail bit detection operation is performed as a brief preliminary check before the main operation, allowing the system to quickly assess memory cell deterioration and adjust parameters accordingly, rather than performing lengthy tests during the main operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the reliability of memory operations by adapting parameters to the deterioration state of memory cells, improving the efficiency and effectiveness of read, program, and erase operations.
Implementation Method 1
sensing a cell current of the selected memory cell to detect a time until the cell current exceeds a reference current
Data Source
AI summary
The present technology relates to an electronic device. According to the present technology, a memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may perform a fail bit detection operation on memory cells selected from among the plurality of memory cells. The control logic may control the peripheral circuit to set target parameters related to a main operation based on a comparison result between a fail bit detection time measured in the fail bit detection operation and a reference time, and perform the main operation on the selected memory cells based on the target parameters.