Memory System Failover via Backup Region and Redundancy Word Lines
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Solution Overview
Problem
Conventional memory systems lack the ability to recover data in case of uncorrectable error correction codes (UECC), leading to insufficient reliability due to the inability to perform failover functions effectively.
Innovation Solution
A memory system with a backup region and a memory controller that stores data in both selected memory cells and a backup region, replacing defective word lines with redundancy word lines to mitigate data loss and improve reliability by performing failover functions before UECC occurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored only in selected memory cells without backup, then device complexity is reduced, but reliability deteriorates due to inability to perform failover operations
Solution Approach 1:
The memory system is segmented into multiple independent memory devices, each with its own backup region. This allows the system to isolate failures to specific segments and perform failover operations on individual devices without affecting the entire system, thereby improving reliability while managing complexity through modular organization
Solution Approach 2:
The patent implements preliminary action by storing duplicate data in backup regions before failures occur. The memory controller proactively monitors memory cell health and performs failover operations in advance, replacing defective word lines with redundancy word lines before uncorrectable errors occur, thus ensuring reliability without requiring complex real-time intervention systems
2Reliability
If failover operations are performed after UECC occurs, then data loss is minimized, but productivity deteriorates due to system shutdown requirements
Solution Approach 1:
The memory controller performs preliminary failover operations by monitoring memory cell status and transferring data to backup regions before UECC occurs. This proactive approach ensures data integrity is maintained while allowing the system to continue operating without shutdown, thus preserving productivity
Solution Approach 2:
The backup region serves as an intermediary storage area that facilitates seamless failover operations. When defects are detected, the controller uses the backup region as a temporary holding area for data migration, enabling continuous system operation and maintaining productivity while ensuring data integrity through the intermediary buffer
3Reliability
If redundancy word lines are not implemented, then device complexity is reduced, but reliability deteriorates due to inability to replace defective word lines
Solution Approach 1:
The patent applies local quality by implementing redundancy word lines specifically in backup regions where they are most needed for failover operations. This targeted approach provides reliability enhancement only where required, rather than uniformly across the entire memory system, thus managing device complexity while improving reliability at critical locations
Solution Approach 2:
The system uses copying by creating redundancy word lines that are copies of original word lines and storing duplicate data in backup regions. This copying mechanism enables the system to replace defective word lines with their redundant copies, ensuring reliability while keeping the complexity manageable through straightforward duplication strategies
Data Source
AI summary
A memory system includes a plurality of memory devices, each of the plurality of memory devices including a plurality of memory cells, and at least one of the plurality of memory devices including a backup region, and a memory controller configured to store data to be stored in a plurality of selected memory cells in the plurality of selected memory cells and the backup region, the plurality of selected memory cells being connected to a selected word line of a selected memory device among the plurality of memory devices, and replace the selected word line with a redundancy word line to which a plurality of redundancy memory cells among the plurality of memory cells are connected in response to a correctable error correction code (CECC) occurring in at least one of the plurality of selected memory cells.