Memory Failure Address Isolation Without SMM Performance Loss
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Solution Overview
Problem
Conventional methods for processing memory failures, such as triggering a System Management Interrupt (SMI) or requiring hardware modifications, lead to system performance degradation and inconvenience.
Innovation Solution
A memory failure processing method that includes acquiring correctable error information, performing out-of-band memory failure prediction, determining whether to trigger a system control interrupt, and performing address isolation using a Platform Runtime Mechanism (PRM) technology, without entering the System Management Mode (SMM) or necessitating hardware changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a System Management Interrupt (SMI) is triggered to process memory errors, then the CPU enters System Management Mode (SMM) for error processing, but system performance is degraded
Solution Approach 1:
The patent segments the memory error processing function from the main CPU execution path by introducing a separate error collection module that operates independently. The CPU continues normal operations while the error module collects and processes memory errors separately, preventing performance degradation.
Solution Approach 2:
The patent introduces an intermediary error collection module that acts as a buffer between the memory error detection and the PRM processing mechanism. This intermediary captures errors and transfers them to the PRM module, which then handles the actual processing without requiring CPU intervention or SMM entry.
2Productivity
If hardware modifications are made to connect the CPU's Error pin to GPIO of the Platform Controller Hub (PCH) to generate System Control Interrupt (SCI), then error processing can be done without entering SMM, but implementation becomes inconvenient
Solution Approach 1:
The patent replaces the mechanical hardware modification approach with a software-based solution. Instead of physically connecting Error pins to GPIO, the invention uses a software error collection module that intercepts memory errors through software mechanisms and processes them via the PRM interface, eliminating the need for hardware changes.
3Reliability
If out-of-band memory failure prediction is performed according to correctable error information, then memory failures can be predicted and addressed proactively, but additional processing steps are required
Solution Approach 1:
The error collection module automatically performs out-of-band memory failure prediction by analyzing collected correctable errors without requiring external intervention. The module self-manages the prediction process, generating risk assessments and triggering appropriate responses based on the analysis results.
Data Source
AI summary
The present application relates to a memory failure processing method and apparatus, and a computer device and a storage medium. The method includes: acquiring correctable error information of a memory; performing an out-of-band memory failure prediction operation according to the correctable error information; according to a prediction result, determining whether to trigger a system control interrupt; in response to the system control interrupt, calling a PRM processing module to acquire memory failure address information corresponding to the triggering of the system control interrupt; and performing an address isolation operation according to the memory failure address information.