Memory Device Failure Mode Analysis via Core-Gap Grouping
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Solution Overview
Problem
Current failure mode analysis methods for semiconductor devices are time-consuming and costly, relying heavily on physical failure analyses that increase manufacturing costs and decrease yield rates.
Innovation Solution
A failure mode analysis method that predicts the failure process site by scanning wafers, generating failure patterns, and grouping single-bits into core and gap groups in self-aligned double patterning processes, allowing for statistical analysis and subsequent physical failure analysis only when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical failure analysis (PFA) is performed to confirm failure modes, then measurement precision and reliability are improved, but loss of time and manufacturing cost increase significantly
Solution Approach 1:
The patent performs preliminary statistical analysis on wafer-level failure data before conducting physical failure analysis. By analyzing failure patterns, single-bit grouping, and process correlation in advance, the system identifies high-probability failure modes and locations, enabling targeted PFA that requires less time while maintaining high identification accuracy.
Solution Approach 2:
The patent segments the failure analysis process into two distinct phases: (1) statistical analysis phase that processes wafer-level data to identify failure patterns and predict failure modes, and (2) physical failure analysis phase that focuses only on predicted failure cases. This segmentation eliminates the need to perform time-consuming PFA on all failures, significantly reducing total analysis time while maintaining precision.
2Reliability
If physical failure analysis (PFA) is performed to confirm failure modes, then reliability of failure identification is improved, but manufacturing cost increases
Solution Approach 1:
The patent applies partial action by performing statistical analysis on the entire wafer dataset to identify failure patterns, but only performs expensive physical failure analysis on a selected subset of cases with high predicted failure probability. This partial application of PFA maintains reliability for the most critical cases while avoiding unnecessary costs for low-probability cases.
Solution Approach 2:
The patent substitutes the mechanical/resource-intensive physical failure analysis process with a computational statistical analysis system for the initial failure mode identification. By using algorithms to analyze failure patterns, single-bit grouping, and process correlation, the system replaces much of the manual, resource-heavy PFA work with automated computational methods, reducing manufacturing costs while maintaining reliability.
3Measurement precision
If comprehensive physical failure analysis is conducted on all failures, then measurement precision is improved, but productivity of the manufacturing process decreases
Solution Approach 1:
The patent performs preliminary statistical analysis to predict failure modes and locations before final confirmation. This preliminary action filters out low-probability cases, allowing the manufacturing process to focus resources on high-priority failures and maintain higher overall productivity while still achieving accurate identification of critical failure modes.
Solution Approach 2:
The patent segments failures into different priority levels based on statistical analysis results. High-priority failures that match predicted failure patterns undergo detailed physical analysis, while low-priority cases are handled more efficiently or through alternative methods. This segmentation maintains measurement precision for critical cases while improving overall manufacturing productivity.
Data Source
AI summary
Provided is a failure mode analysis method for a memory device including the following steps. A wafer is scanned by a test system to generate a failure pattern of the wafer, and a failure count of a single-bit in the wafer is obtained by a test program. A single-bit grouping table is defined according to a word-line layout, a bit-line layout, and an active area layout. A core group and a gap group are formed through grouping in at least one process in a self-aligned double patterning process. Failure counts of single-bits in the core group and the gap group are respectively counted to generate core failure data and gap failure data.