Memory Failure Forcing Circuit for Redundant Column Repair Testing
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Solution Overview
Problem
Existing memory devices face inefficiencies in detecting and repairing defective rows and columns without relying on actual failed components, necessitating a method to test the controller's ability to detect and repair such defects proactively.
Innovation Solution
The implementation of a disable control circuit that forces specific memory failures by altering access operations, including suppressing internal control signals, blocking data paths, and modifying read bits, allowing the memory device to simulate defects and test its repair capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory device relies on actual failed rows and columns to test repair capabilities, then the testing process becomes unpredictable and time-consuming, but the device cannot proactively evaluate its repair functionality
Solution Approach 1:
The disable control circuit pre-configures specific memory locations as disable rows or columns before actual failures occur. When a read operation targets these pre-designated locations, the circuit forcibly disables the operation to simulate failures, allowing proactive testing of repair capabilities without waiting for unpredictable actual failures
Solution Approach 2:
The circuit applies preliminary anti-action by intentionally preventing read operations at pre-selected memory locations before actual failures occur. This proactive disabling creates controlled failure scenarios that allow the system to test and validate its repair mechanisms in advance, rather than reacting to unexpected failures
2Productivity
If the memory device waits for actual failures to occur before testing repair operations, then no additional testing circuitry is needed, but the testing efficiency and productivity are reduced
Solution Approach 1:
The disable control circuit integrates multiple functions into a single component: it stores disable location information, determines whether read operations target disabled locations, generates disable signals to force failures, and enables proactive testing of repair capabilities. This multi-functionality achieves efficient testing without proportionally increasing device complexity
Solution Approach 2:
The circuit merges the testing functionality with the existing read operation infrastructure by integrating the disable control logic into the normal memory access path. The same control circuitry that manages read operations also handles failure simulation and repair testing, combining multiple functions without requiring completely separate testing hardware
3Reliability
If the memory device uses redundant rows and columns for repair operations, then defective memory can be recovered, but the overall memory capacity is reduced
Solution Approach 1:
The system performs preliminary identification and designation of redundant rows and columns before actual failures occur. By pre-configuring which memory locations serve as backups and establishing disable locations in advance, the system optimizes the utilization of redundant resources, ensuring they are effectively positioned to cover potential failures without excessive overhead
Solution Approach 2:
The circuit implements feedback by continuously monitoring read operations against the stored disable location information. When a read operation targets a disabled location, the circuit generates a disable signal that prevents the operation, allowing the system to detect and trigger repair operations. This feedback mechanism ensures redundant resources are activated only when needed, optimizing their utilization
Data Source
AI summary
Apparatuses and methods for forcing memory cell failures in a memory device are disclosed. An example apparatus includes a column disable control circuit coupled to a plurality of column latch sets to receive match signals and associated column plane addresses, the column disable control circuit configured to provide redundant column select signals and column plane masking signals based on the match signals and associated column plane addresses, the column disable control circuit further configured to provide the redundant column select signal and the column plane masking signal corresponding to an active match signal and associated column plane address from a designated column latch set when a disable memory test mode is enabled to cause one or more memory cells of main memory to fail.