Electronic Device Memory Fast Data Storage Allocation

The patent segments the memory space into multiple regions: a first memory region for high-density storage and a second memory region for low-density fast storage. This segmentation allows the system to simultaneously maintain large storage capacity through high-density regions while achieving fast data storage speed through low-density regions, thereby resolving the contradiction between storage capacity and data storage speed.

The patent applies different storage modes to different local regions of the memory. The first memory region uses high-density storage mode for capacity, while the second memory region uses low-density storage mode for speed. This local differentiation of storage characteristics allows the system to optimize both capacity and speed in their respective regions, resolving the fundamental trade-off.

The patent implements a feedback mechanism where the processor receives information about the size of the allocated second memory region from the memory management unit. This feedback allows the processor to accurately identify the allocated space and avoid generating write I/O requests that would interfere with the fast storage operations, thereby preventing data processing delays while maintaining high storage speed.

The patent introduces a memory management unit as an intermediary between the processor and the memory regions. This intermediary manages and tracks the allocation of the second memory region for fast storage, providing accurate size information to the processor and coordinating access to prevent conflicts, thus resolving the identification problem and processing delays.