Memory Device Fault Detection via Address Comparison
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Automotive electronic systems face challenges in detecting faults in memory devices, particularly for high safety integrity levels like ASIL-D, due to limited testing opportunities after installation in vehicles, which can impact operational reliability and safety.
Innovation Solution
A memory device with fault detection functionality is introduced, featuring a first and second memory cell array, a control logic block, and a comparator. The memory device stores and compares address signals during write and read operations, providing an address comparison signal to detect potential faults, ensuring compliance with ASIL-D safety standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a memory device is tested at wafer level before mounting, then manufacturing precision is improved, but the ability to detect faults after installation deteriorates
Solution Approach 1:
The patent implements preliminary action by storing copy address signals in the second memory cell array before actual memory operations. This allows the system to have detection capability ready in advance, enabling fault detection during normal read/write operations without requiring separate post-installation testing procedures.
Solution Approach 2:
The patent creates a copy of the address signals and stores them in a separate second memory cell array. This copying mechanism enables comparison between the original address signals and stored copies to detect faults, allowing post-installation fault detection without interfering with the primary memory function.
2Reliability
If fault detection functionality is added to the memory device, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the fault detection function with the existing memory device structure by using the second memory cell array that already exists for other purposes. The address comparison logic is integrated into the control circuitry, combining multiple functions into existing components rather than adding separate dedicated fault detection hardware.
Solution Approach 2:
The second memory cell array serves multiple functions: it stores copy address signals for fault detection, and simultaneously serves as functional memory space that can be accessed by the processor. This multi-functionality reduces the need for dedicated fault detection hardware, thereby limiting the increase in device complexity.
3Measurement precision
If address signals are stored in a separate memory array for comparison, then fault detection precision is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the memory device into two distinct memory cell arrays: the first memory cell array for primary data storage and the second memory cell array for storing copy address signals. This segmentation allows each array to be optimized for its specific function while maintaining a relatively simple overall manufacturing process using standard memory fabrication techniques.
Data Source
AI summary
A memory device having fault detection functionality for improving functional safety and a control system including the memory device are provided. The memory device includes a first memory cell array configured to store input data and output the input data as output data and a second memory cell array configured to store bit values of a row address and a column address of the first memory cell array in which the input data is stored, and output the bit values of the row address and the column address as an internal row address and an internal column address. The row/column address designating a read operation may be compared to the internal row/column address, and an address comparison signal as a result of the comparison may be output. The address comparison signal may provide fault detection functionality for a data error of an automotive electronic system.