Memory Fault Analysis Using Cell-Block Architecture Boundaries
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Solution Overview
Problem
Existing methods for predicting uncorrectable errors (UEs) in memory devices have low prediction rates due to varying device architectures and low correlation with correctable errors (CEs), leading to server failures and downtime.
Innovation Solution
A fault analysis device and memory system that analyzes faults by accumulating error information and reflecting device information, including architectural and data input/output information, to specify fault boundaries and improve UE prediction rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If prediction methods based on CE occurrences or system address are used, then the analysis process is simple, but the prediction rate of UEs is low
Solution Approach 1:
The memory device is segmented into multiple cell blocks with specific architectural characteristics (shared word line drivers, shared bit line sense amplifiers). The fault analysis device segments the error information analysis by reflecting device information for each cell block, enabling precise identification of fault boundaries within specific cell blocks rather than treating the memory device as a whole.
Solution Approach 2:
The patent applies local quality by using device information that is specific to each cell block's architecture. The fault analysis device reflects device information including architectural information on cell blocks to identify fault boundaries locally within specific cell blocks, rather than applying a uniform analysis approach across the entire memory device.
2Reliability
If generic prediction methods are used, then the implementation is easy, but the correlation with CEs is low
Solution Approach 1:
The patent implements preliminary action by accumulating error information and reflecting device information before fault occurrence. The fault analysis device accumulates error information from the memory device and reflects device information including architectural information on cell blocks in advance, enabling proactive identification of fault boundaries and prediction of potential UEs before they occur.
Solution Approach 2:
The patent applies feedback by using accumulated error information to identify fault boundaries and predict UEs. The fault analysis device accumulates error information from the memory device, reflects device information onto the accumulated error information, and uses this feedback loop to continuously improve fault prediction accuracy based on actual error patterns observed in specific cell blocks.
Data Source
AI summary
A memory system includes at least one memory device disposed along a first direction and a second direction, configured to include a plurality of cell blocks that share word line drivers with adjacent cell blocks in the first direction, to share bit line sense amplifiers with adjacent cell blocks in the second direction, and to input/output data of the plurality of cell blocks through a plurality of data pads; and a fault analysis device configured to analyze a fault of the memory device by accumulating an error information from the memory device and reflecting device information, including architectural information on the plurality of cell blocks and data input/output information, onto the accumulated error information.