Memory Fault Detection Circuitry for Parallel Access and Area Reduction
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Solution Overview
Problem
Existing fault detection methods face challenges in minimizing both computation time and implementation area, with centralized architectures being slow due to sequential processing and distributed architectures being area-intensive due to multiple processor instances and interconnect circuitry requirements.
Innovation Solution
The proposed fault detection circuitry employs a single instance of processor circuitry with converter circuitry to convert instructions into specific memory formats, enabling parallel access and combining results through interconnect circuitry that satisfies power safety thresholds, thereby reducing computation time and implementation area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If centralized architecture is used for fault detection, then implementation area is reduced, but computation time increases due to sequential processing
Solution Approach 1:
The patent segments the fault detection process by dividing memory circuits into multiple banks and implementing separate processor instances for each bank. This allows parallel processing of different memory banks simultaneously, reducing overall computation time while maintaining a compact implementation area through specialized modular processor design.
Solution Approach 2:
The patent transitions from a single-dimension sequential processing architecture to a multi-dimensional parallel architecture by adding the dimension of concurrent processor operation. Multiple processor instances operate simultaneously on different memory banks, transforming the time-computation sequence into a spatially distributed parallel computation model.
2Loss of time
If distributed architecture is used for fault detection, then computation time is reduced through parallel processing, but implementation area increases due to multiple processor instances and interconnect circuitry
Solution Approach 1:
The patent applies local quality by designing specialized processor instances that are optimized for specific memory bank characteristics. Each processor instance is tailored to its associated memory bank's protocol and access patterns, improving processing efficiency locally while reducing the need for complex universal interconnect circuitry.
Solution Approach 2:
The patent extracts and eliminates redundant interconnect circuitry by directly coupling processor instances to their associated memory banks. This removal of unnecessary intermediary connection logic reduces implementation area while maintaining the parallel processing benefits of the distributed architecture.
3Adaptability or versatility
If multiple memory circuits with different protocols are accessed, then memory characterization capability is improved, but instruction conversion complexity increases
Solution Approach 1:
The patent implements universality by designing processor instances with multi-functional instruction conversion capabilities. Each processor instance can convert instructions to multiple different memory protocols, eliminating the need for separate dedicated conversion circuitry for each memory type and reducing overall system complexity.
Solution Approach 2:
The patent merges the instruction conversion function directly into the processor instance logic, combining what would traditionally be separate conversion and processing units. This integration simplifies the overall architecture by eliminating intermediate conversion stages and reducing the number of discrete components required.
Data Source
AI summary
An example device includes: converter circuitry having an output configured to couple to a first memory circuit from a plurality of memory circuits, the converter circuitry configured to: receive a first instruction formatted with a uniform protocol; and convert the first instruction from the uniform protocol to a protocol specific to the first memory circuit; logic circuitry having an input configured to couple to the first memory circuit, the logic circuitry configured to: receive a first result of the first instruction from the first memory circuit; and responsive to a second instruction, combine the first result with other results from ones of the plurality of memory circuits into an output.