Hierarchical Memory Fault Diagnosis Using Segmented Row and Cell Areas
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Solution Overview
Problem
Existing memory fault diagnostic methods for safety instrumentation systems are inefficient as they require extensive read and write operations, leading to increased processing time with larger memory capacities, particularly due to the lack of effective hierarchical diagnosis approaches.
Innovation Solution
A memory fault diagnostic method that divides the diagnosis area into non-overlapping Row areas and Cell areas, performing two hierarchical diagnostic steps: one within Row areas and another between Row areas, to minimize diagnostic time by optimizing the size of these areas and reducing the number of memory access combinations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Walkpath or GALPAT algorithms are used to detect coupling faults in the whole memory area, then fault detection capability is improved, but the number of read and write operations increases proportionally to the square of memory size, causing diagnostic time to increase
Solution Approach 1:
The memory area is divided into multiple sub-areas (first memory area, second memory area, etc.), and diagnosis is performed hierarchically. First, high-order address bits are tested across different memory areas, then low-order address bits are tested within selected sub-areas. This segmentation reduces the number of required read/write operations from proportional to the square of total memory size to a manageable level while maintaining coupling fault detection capability.
Solution Approach 2:
The patent introduces a hierarchical dimension to the diagnosis process by separating address bits into high-order and low-order groups, and organizing memory access patterns across multiple dimensions (area selection, row selection, column selection). This multi-dimensional approach allows comprehensive fault detection with reduced operation count compared to traditional single-dimension Walkpath methods.
2Productivity
If hierarchical diagnosis area is set to reduce memory access times, then processing time is shortened, but the complexity of area division and diagnostic steps increases
Solution Approach 1:
The memory is segmented into multiple areas with clear hierarchical structure (first memory area, second memory area, etc.), where each area can be independently diagnosed. This segmentation enables parallel or sequential diagnosis of smaller units, reducing total processing time while maintaining organized, manageable complexity through systematic area division.
Solution Approach 2:
The patent performs preliminary classification of memory areas based on high-order address bit testing before proceeding to detailed low-order address bit testing within selected areas. This preliminary action identifies problematic regions early, allowing focused diagnosis on only those areas that require detailed testing, thereby reducing overall processing time and complexity.
Data Source
AI summary
An area of a memory has a diagnosis area and a non diagnosis area, with the diagnosis area divided into a plurality of Row areas which do not overlap each other, and each of the Row areas is divided into a plurality of Cell areas which do not overlap each other. A memory fault diagnostic method has a diagnostic step in a Row area to diagnose between Cell areas with respect to all the combinations of a set of Cell areas in the Row area, and a diagnostic step between Row areas to diagnose between Row areas with respect to all the combinations of a set of Row areas in the diagnosis area. A Row area size is determined to be a size in which a time of the diagnosis in a Row area becomes equal to a time of the diagnosis between Row areas.