Memory Fault Early-Warning via Correctable Error Isolation
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Solution Overview
Problem
Existing server systems face challenges in effectively detecting and correcting uncorrectable memory errors (UCEs), which can lead to data loss and system crashes such as kernel panic, due to the inability to suppress their occurrence.
Innovation Solution
A method and apparatus for memory fault early-warning that involves collecting information on correctable errors (CEs), determining executable pages based on error thresholds, and performing memory fault isolation to reduce the likelihood of UCEs by identifying and isolating affected memory pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory error correction codes (ECC) are used to correct correctable errors (CE), then memory reliability is improved, but uncorrectable errors (UCE) still occur and cause system crashes
Solution Approach 1:
The patent applies preliminary action by monitoring correctable errors (CE) before they can evolve into uncorrectable errors (UCE). When a memory cell reaches a predetermined number of CE occurrences, the system proactively isolates the affected memory page, preventing future UCEs from causing system crashes. This early warning and isolation mechanism addresses the harmful effect before it materializes.
Solution Approach 2:
The patent extracts the problematic memory page from the active memory space by isolating it when excessive CEs are detected. This separation removes the harmful element (memory page with high error rate) from the system's active memory operations, preventing it from causing UCE-induced crashes while preserving the rest of the memory system's functionality.
2Stability of the object's composition
If memory fault isolation is performed on executable pages, then system stability is improved, but memory access performance deteriorates
Solution Approach 1:
The patent applies local quality by isolating only the specific memory pages that exhibit excessive error rates, rather than isolating all memory pages. This targeted approach maintains system stability for the affected local regions while preserving normal memory access performance for the rest of the memory space, minimizing the overall impact on productivity.
Solution Approach 2:
The patent implements partial action by isolating memory pages based on a predetermined threshold of CE occurrences. Not all memory pages with occasional errors are isolated, only those exceeding the threshold, thereby achieving sufficient stability protection without excessive isolation that would harm memory access performance.
3Measurement precision
If CE information is statistically collected and analyzed, then error detection accuracy is improved, but system complexity increases
Solution Approach 1:
The patent applies self-service by implementing an automated error monitoring and analysis mechanism that operates autonomously within the memory subsystem. The system self-monitors CE occurrences, statistically analyzes error patterns, and autonomously determines when isolation is needed, reducing the need for external intervention and managing complexity internally.
Solution Approach 2:
The patent implements feedback by continuously monitoring CE occurrences and using this information to adjust memory page isolation decisions. The system feeds back error statistics to the isolation determination logic, creating a closed-loop control mechanism that improves error detection accuracy while managing complexity through automated feedback-driven decision-making.
Data Source
AI summary
A memory fault early-warning method and apparatus, and an electronic device and a non-transitory computer-readable storage medium. The method includes: when a Correctable Error (CE) occurs in a memory cell, statistically collecting information of the CE; when the number of times that the CE occurs in the memory cell reaches a reset threshold, determining, as an executable page, a memory page in which the memory cell is located, or when the information of the CE meets an error determination condition of a memory row address, determining, as the executable page, a memory page associated with a memory row in which the memory cell is located; and performing memory fault isolation on the executable page.