Memory Controller Fault Detection for Correctable Error Conversion
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Solution Overview
Problem
Current memory devices face challenges in precisely detecting and correcting permanent faults, which can lead to errors in memory modules due to faulty memory chips or data paths, affecting multiple bits across identical locations, thus requiring improved error correction reliability.
Innovation Solution
A memory controller with a fault detector that includes inverters, buffers, an XOR operator, and an error pattern change unit to identify faulty addresses and convert uncorrectable errors into correctable errors, enhancing error correction capabilities by performing XOR operations and data inversion to generate faulty address information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods are used, then basic error correction is provided, but error correction reliability is insufficient for permanent faults affecting multiple bits
Solution Approach 1:
The fault detection process is segmented into multiple independent stages: initial error detection, faulty address identification through XOR operations, and separate error pattern conversion. This segmentation allows precise localization of faults to specific addresses while maintaining overall system reliability.
Solution Approach 2:
The system performs preliminary fault detection and address identification before final error correction. By pre-identifying faulty addresses and converting error patterns in advance, the system prepares correction data that enhances reliability when permanent faults occur.
2Measurement precision
If simple error detection is used, then device complexity is low, but fault detection precision is insufficient for identifying specific faulty addresses
Solution Approach 1:
The fault detector is divided into specialized functional units: XOR operators for address identification, inverters for data transformation, and separate error pattern conversion units. Each unit performs a specific function, enabling precise faulty address identification while keeping individual components relatively simple.
Solution Approach 2:
The XOR operator acts as an intermediary that compares read data with inverted read data to identify faulty addresses. This intermediary mechanism translates complex fault patterns into identifiable address information without requiring the entire system to handle all complexity simultaneously.
3Reliability
If uncorrectable errors are directly handled, then error correction process is simple, but error correction reliability is low for permanent faults
Solution Approach 1:
The system converts uncorrectable error patterns into correctable error patterns by inverting read-out inverted read data and applying error pattern conversion. This transformation turns harmful uncorrectable errors into beneficial correctable errors that can be reliably fixed, enhancing overall error correction reliability.
Solution Approach 2:
The error pattern conversion unit changes the parameters of error patterns by inverting bits and transforming uncorrectable patterns into correctable ones. This parameter transformation allows the error correction system to handle permanent faults that would otherwise be uncorrectable.
Data Source
AI summary
A memory device includes; a memory module including a memory array, and a memory controller that retrieves read data from memory cells of the memory array. The memory controller includes a fault detector that detects faulty addresses associated with faulty memory cells among the memory cells providing data errors. The fault detector includes; a first inverter that generates inverted read data by reading and inverting the read data, wherein the inverted read data is stored in the memory array, a first buffer that stores the read data and provides buffered data, an XOR operator that receives the buffered data from the first buffer, receives read-out inverted data generated by reading the inverted read data stored in the memory array, and performs an XOR operation on the buffered data and the read-out inverted read data to generate calculation data, a fault address detection unit that identifies the faulty addresses in response to the calculation data and generates faulty address information, a second inverter that generates inverted read-out inverted read data by receiving and inverting the read-out inverted read data, and an error pattern change unit that converts an uncorrectable error (UE)-causing data into a correctable error (CE)-causing data.