Memory Fault Logging Circuit for Multi-Row Error Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory device capacities increase, it becomes increasingly difficult to fabricate memory devices without defective memory cells, and existing solutions like redundant cell repair and error correction circuits do not efficiently manage multi-row faults during error logging operations.
Innovation Solution
A memory device with a fault detection circuit and fault information management circuit that identifies and logs multi-row faults by generating and storing fault addresses, updating fault mode information, and providing error information to enhance reliability, accessibility, and serviceability (RAS) operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction circuits and redundant memory cells are used to repair defective memory cells, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the error logging function from the existing error correction circuitry and implements it as a separate fault information management circuit. This allows the error correction functionality to remain while adding specialized multi-row fault detection and logging capabilities without unnecessarily increasing the overall device complexity
Solution Approach 2:
The fault information management circuit segments the error handling process into distinct functional components: fault detection, fault address storage, fault mode determination, and error information output. This segmentation allows each component to be optimized independently and simplifies the overall system architecture
2Reliability
If existing error logging operations are used, then single row faults can be detected, but multi-row faults cannot be properly identified and logged
Solution Approach 1:
The fault information management circuit is designed to handle multiple types of faults (single row faults and multi-row faults) using a unified approach. The circuit universally processes fault addresses and automatically determines fault modes, making it adaptable to different fault scenarios without requiring separate detection mechanisms for each fault type
Solution Approach 2:
The circuit dynamically determines fault modes based on the relationships between fault addresses. By analyzing whether fault addresses belong to the same row or different rows, the system adapts its behavior to correctly identify and log the appropriate fault type, transitioning from static single-row detection to dynamic multi-row detection
Data Source
AI summary
A memory device includes a memory cell array including memory cells coupled to a plurality of rows; a fault detection circuit configured to generate first to third fault addresses according to a result of an error check operation for each of the plurality of rows and sequentially outputs the first to third fault addresses together with a fault input signal; and a fault information management circuit configured to store the first fault address as a start fault address and generate fault mode information that defines a relationship between the stored start fault address and the second and third fault addresses, according to the fault input signal, and output error information including the start fault address and the fault mode information.