Memory Fault Patching via Hierarchical Cache Redirection
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Solution Overview
Problem
The increasing transistor density in processors leads to power dissipation issues, including local thermal hot-spots and global power dissipation problems, which can cause memory errors and require costly solutions like redesigning memory circuits or incorporating redundancy.
Innovation Solution
The use of pre-existing memory structures, such as miss-status handling registers and hierarchical cache structures, to patch intermittent memory faults by redirecting memory accesses and increasing data persistence in redundant storage, thereby leveraging natural redundancy without significant cost impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage-dependent error mitigation techniques are used (redesigning memory circuits with more transistors), then memory reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent introduces an intermediary component (error mitigation circuitry) that sits between the memory circuits and the processing unit. This circuitry intercepts memory access requests, detects voltage-dependent errors, and retrieves correct data from alternative sources (other memory banks or higher-level cache), thereby protecting the system from errors without requiring the entire memory system to be redesigned with more complex circuits.
Solution Approach 2:
The error mitigation circuitry serves multiple functions: it monitors for voltage-dependent errors, manages alternative data sources, handles error correction, and maintains normal memory operation. This multi-functional approach allows a single added component to address reliability issues without proportionally increasing overall system complexity.
2Reliability
If redundancy is incorporated into memory circuits (additional error correcting codes), then memory reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
Rather than embedding redundancy directly into the memory circuits themselves, the patent uses an intermediary error mitigation circuitry that manages redundancy externally. This circuitry accesses alternative memory banks or higher-level cache structures to retrieve backup data when errors are detected, avoiding the need to duplicate memory circuits within each bank.
Solution Approach 2:
The system utilizes existing copies of data that already exist in the memory hierarchy (in other banks or in higher-level cache) rather than creating additional redundant copies specifically for error correction. This approach leverages naturally occurring data copies to provide fault tolerance without adding dedicated redundancy circuits.
3Reliability
If transistor size is increased to reduce process variation, then memory reliability is improved, but power density and global power dissipation worsen
Solution Approach 1:
The patent segments the memory system into multiple independent banks organized in a hierarchy. By dividing the memory into separate banks, the system can isolate voltage-dependent errors to specific banks and retrieve data from other banks without affecting the entire memory system. This segmentation allows smaller transistors to be used in each bank while maintaining overall reliability through the hierarchical structure.
4Power
If operating voltage is reduced to lower power consumption, then power dissipation is improved, but memory reliability deteriorates due to voltage-dependent errors
Solution Approach 1:
The error mitigation circuitry acts as an intermediary that enables the system to operate at lower voltages while maintaining reliability. By monitoring for voltage-dependent errors and providing alternative data retrieval paths, this circuitry allows the memory to function reliably at reduced voltage levels where voltage-dependent errors would normally occur.
Solution Approach 2:
The system relies on existing data copies in the memory hierarchy to compensate for voltage-dependent errors that occur at lower operating voltages. When an error is detected in one memory bank operating at reduced voltage, the error mitigation circuitry retrieves the correct data from alternative sources, enabling continued reliable operation at lower power consumption.
Data Source
AI summary
A computer architecture addresses intermittent memory faults by exploiting redundancy inherent in a hierarchical memory structure, for example, as data moves through various cache levels and registers before use by the processor. Accesses to data from faulted memory areas is diverted to a secondary memory structure holding that data and the secondary memory structure is flagged to increase the persistence of the stored data used for patching against normal updating policies.