Memory Fault Prediction Using Correctable Error Patterns
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Solution Overview
Problem
Existing memory devices face challenges in predicting and preventing uncorrectable errors (UE) by aggregating correctable errors (CE) over time, leading to device or system downtime, as current error correction mechanisms are reactive and insufficient to address complex error patterns.
Innovation Solution
Implement predictive fault analysis using manufacturer-specific information and proprietary mappings to identify error patterns, proactively offlining or repairing memory pages susceptible to future errors, thereby preventing UE events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reactive error correction mechanisms are used, then correctable errors can be corrected, but uncorrectable errors cannot be predicted or prevented, leading to device or system downtime
Solution Approach 1:
The patent implements preliminary action by proactively analyzing correctable error patterns before they escalate to uncorrectable errors. The system monitors CE events, identifies spatial and temporal patterns, and preemptively offlines affected memory pages or triggers repairs before UEs occur, thereby preventing downtime rather than reacting to failures after they happen.
Solution Approach 2:
The patent employs feedback mechanisms by continuously monitoring correctable error events and using this information to adjust memory management decisions. The system feeds error pattern information back into the memory control logic to make real-time decisions about page offlining, repair triggering, and memory allocation, creating a closed-loop system that adapts to emerging error patterns.
2Reliability
If memory pages are offlined proactively to prevent future errors, then system reliability is improved, but available memory capacity is reduced
Solution Approach 1:
The patent applies local quality by offlining only the specific memory pages that exhibit error patterns rather than entire memory modules or banks. This localized approach isolates problematic areas while keeping the rest of the memory system operational, thereby maintaining maximum available capacity while still achieving reliability improvements through targeted page offlining.
Solution Approach 2:
The patent implements discarding and recovering by temporarily offlining memory pages that show error patterns (discarding them from active use) and then recovering them through repair processes or reallocation. Once repaired or replaced, the pages are brought back into service, thus temporarily reducing available capacity to prevent errors but ultimately restoring full capacity after remediation.
3Measurement precision
If error patterns are analyzed using manufacturer-specific information and proprietary mappings, then prediction accuracy is improved, but device complexity increases
Solution Approach 1:
The patent uses intermediary structures such as lookup tables, mapping data structures, and pre-computed spatial relationships that translate complex manufacturer-specific physical mappings into simplified error pattern analysis. These intermediaries act as mediators between the raw manufacturer data and the analysis logic, improving measurement precision while shielding the system from the full complexity of proprietary mappings.
Data Source
AI summary
Correctable error pattern information for a memory device can be based on data received from or using a data pin of the memory device. The memory device can include, for example, a DRAM device comprising an array of memory cells. Based on the error pattern information, firmware or software can be used to identify respective physical portions of the array comprising data with correctable errors. In an example, one or more fault locations in the memory device can be identified, the fault location corresponding to multiple cells in the array and comprising the data with correctable errors. In response to identifying the fault location in the array, one or more memory pages corresponding to the location(s) can be offlined or removed from an addressable memory space. In an example, the memory device comprises a portion of a compute express link (CXL) system.