Memory Device High Impedance Fault Detection via Supply Line Floating
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Solution Overview
Problem
Memory devices face challenges in detecting high impedance faults between control lines and supply lines, which can lead to errors in activating drivers and accessing memory cells, resulting in unnecessary power consumption and access operation errors.
Innovation Solution
The memory device performs a test operation by floating the supply line between two write operations to detect high impedance faults by writing a first set of data, then attempting a second write operation, and reading the data to determine if a fault exists based on the data read from the memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the supply line is continuously connected to the voltage source during memory operations, then normal read/write operations can be performed, but high impedance faults between control lines and supply lines cannot be detected
Solution Approach 1:
The patent applies preliminary action by performing a test operation before normal memory operations to detect high impedance faults. The test operation floats the supply line between two write operations and attempts to write test data, thereby identifying faults before they affect normal memory functionality. This preliminary detection mechanism resolves the contradiction by enabling fault detection without compromising normal operations.
Solution Approach 2:
The patent maintains continuity of useful action by integrating the fault detection test into the existing memory operation sequence. The test operation is inserted between two write operations, allowing the supply line to be floated temporarily for fault detection while maintaining continuous memory operation capability. This approach enables fault detection without interrupting the overall memory system functionality.
2Reliability
If a test operation is performed by floating the supply line between write operations, then high impedance faults can be detected, but additional time is required for the test operation
Solution Approach 1:
The patent merges the fault detection test with existing memory write operations by positioning the test between two consecutive writes. The test operation uses the same write logic and data paths as normal operations, combining fault detection functionality with existing memory operations. This merging approach minimizes additional time requirements while maintaining accurate fault detection capability.
Solution Approach 2:
The patent implements periodic action by performing the fault detection test at regular intervals between memory write operations. Rather than continuously testing or testing only at specific moments, the test is periodically inserted into the memory operation sequence, balancing detection accuracy with time efficiency. This periodic approach ensures faults are detected without excessively increasing overall operation time.
3Reliability
If the supply line is floated between write operations, then high impedance faults can be identified, but the memory operation sequence becomes more complex
Solution Approach 1:
The patent applies self-service by using the memory device's own write operations and data paths to perform the fault detection test. The test utilizes existing write logic, data buses, and memory cells without requiring external test equipment or complex additional circuitry. This self-service approach simplifies operation by leveraging existing components to perform both normal operations and fault detection.
Solution Approach 2:
The patent implements universality by designing the test operation to use the same hardware resources and control logic as normal memory operations. The write logic, data paths, and memory cells serve dual purposes: normal memory operations and fault detection testing. This multi-functionality reduces operational complexity by avoiding dedicated test hardware and simplifying the control sequence.
Data Source
AI summary
Methods, systems, and devices related to identifying high impedance faults in a memory device are described. A memory device may perform a first write operation to write a first logic state to a memory cell. During the first write operation, the memory device may establish a connection between a supply line and a control line associated with applying an output of a driver of a digit line coupled to the memory cell. After performing the first operation, the memory device may configure the supply line in a floating state. After the supply line is floated, the memory device may perform a second write operation to write a second logic state to the memory cell. The memory device may perform a third operation for reading the memory cell. The memory device may determine the condition of the supply line or control based on the result of the read operation.