Internal Memory Fault Detection Through ECC Write-Back Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing internal memory controllers frequently report errors due to soft failures, leading to increased processor load and unnecessary work, as they fail to distinguish between soft failures and hardware faults accurately.
Innovation Solution
The internal memory controller performs error correction, write-back, and re-reading operations to determine the type of error, reporting only hardware faults, thereby reducing unnecessary error reporting and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the internal memory controller reports all detected errors to the processor, then error detection coverage is improved, but processor load increases and unnecessary work is generated
Solution Approach 1:
The patent extracts and filters out soft failures from the error reporting stream, separating them from hardware faults. The memory controller performs additional verification operations to identify which errors are transient soft failures that should not be reported to the processor, thereby reducing unnecessary processor load while maintaining coverage of actual hardware faults.
Solution Approach 2:
The patent introduces an intermediary verification mechanism between error detection and processor reporting. This intermediary layer performs additional read operations and error analysis to determine whether an error warrants processor notification, acting as a filter that prevents false positives from reaching the processor while ensuring genuine hardware faults are reported.
2Measurement precision
If the internal memory controller performs additional verification operations to distinguish error types, then error reporting accuracy is improved, but system complexity increases
Solution Approach 1:
The patent performs preliminary verification operations immediately upon detecting an error, before deciding whether to report it. This includes conducting additional read operations and analyzing error patterns right at the memory controller level, which prevents unnecessary processor interruptions while accurately identifying hardware faults that require attention.
Solution Approach 2:
The patent implements a feedback mechanism where the memory controller monitors error patterns and verification results to refine its reporting decisions. By analyzing whether corrected data matches expected values and whether errors recur, the system builds feedback loops that improve error classification accuracy without requiring complex external verification systems.
Data Source
AI summary
A hardware fault detection method includes, after performing error correction on data at a target location in an internal memory and writing corrected data into the target location, the internal memory controller reads first data from the target location. When determining that an error exists in the first data, the internal memory controller reports an error message, where the error message indicates that a hardware fault occurs at the target location. After finding that an error occurs in the data at the target location, the internal memory controller performs the error correction, write-back, and re-reading on the data, to further determine a type of the error occurring at the target location.