Memory Transmission Feedback Separation to Reduce EDC Crosstalk

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Solution Overview

Problem

Crosstalk between error detection code (EDC) lines and data lines in memory devices causes increased errors and inefficiencies due to interference, leading to frequent data rewriting and latency issues.

Innovation Solution

Implementing transmission error feedback schemes that transmit error detection information on a line separate from the EDC line and introduce timing offsets to reduce crosstalk, using dedicated channels for error and clock signals to minimize interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error detection information is transmitted on the EDC line concurrently with data, then error detection capability is improved, but crosstalk interference increases causing more errors

Engineering Contradiction:
Improveerror detection capabilityVSAvoidcrosstalk interference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the feedback transmission by separating error detection information from data transmission. A dedicated feedback line is introduced that is physically separate from the data lines and EDC lines, allowing error information to be transmitted without causing crosstalk interference with ongoing data transmissions. This segmentation resolves the contradiction by enabling reliable error detection while eliminating the harmful crosstalk effect.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a feedback line as an intermediary channel. Instead of transmitting error detection information directly on the EDC line (which causes crosstalk), the feedback line serves as a mediator that carries error information separately. This intermediary approach allows the EDC line to function for error detection without being contaminated by feedback signal crosstalk, thus resolving the interference problem while maintaining detection capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If frequent error detection feedback is transmitted, then error detection reliability is improved, but latency and rewriting operations increase

Engineering Contradiction:
Improveerror detection reliabilityVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements periodic action by transmitting error detection information only at specific intervals rather than continuously. The feedback is sent periodically based on transmission conditions, allowing error detection to occur at optimal moments without constant interruption to data flow. This periodic approach maintains detection reliability while minimizing the time loss associated with frequent feedback transmissions and subsequent rewriting operations.

Inventive Principle:
Principle #19Periodic action

3Speed

If EDC signaling is transmitted at high speed, then error detection responsiveness is improved, but crosstalk to data lines increases

Engineering Contradiction:
Improveerror detection responsivenessVSAvoidcrosstalk to data lines
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent segments the signal transmission paths by providing a dedicated feedback line that is physically separated from the data lines. This allows high-speed error detection feedback to be transmitted on the feedback line without generating crosstalk on the data lines. The segmentation isolates the harmful electromagnetic interference, enabling fast responsive error detection while preventing crosstalk contamination of the data transmission medium.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3841473B1Transmission failure feedback schemes for reducing crosstalk
Publication Date: 2025.07.09 MICRON TECHNOLOGY INC
  • EP3841473B1 patent drawingFigure 1
  • EP3841473B1 patent drawingFigure 2
  • EP3841473B1 patent drawingFigure 3

AI summary

Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.