Memory Interface Feedback Sampling for DDR Signal Eye Measurement

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Solution Overview

Problem

Current DDR SDRAM memory designs face challenges in measuring signal quality and integrity due to increasing clock frequencies and signal edge rates, requiring complex and inconvenient external oscilloscope measurements for valid data width assessment.

Innovation Solution

A memory circuit with a feedback path and adjustable phase clock signal, allowing the memory controller to generate and analyze a feedback signal in response to a variable reference voltage, enabling the creation of an eye diagram to determine signal quality without relying on external devices or response signals from the memory device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If external oscilloscope measurements are used to assess signal quality, then measurement capability is provided, but device complexity and measurement convenience deteriorate

Engineering Contradiction:
Improvesignal quality measurementVSAvoidmeasurement system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a feedback path as an intermediary component that captures the output signal and feeds it back to the memory controller. This feedback path acts as a mediator that enables internal signal quality measurement without requiring external oscilloscope equipment, thereby reducing device complexity while maintaining measurement precision

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The memory controller performs signal quality measurement on its own output signal through the feedback path, enabling self-service measurement capability. The system measures its own signal integrity internally using the feedback mechanism, eliminating the need for external measurement devices and improving measurement convenience

Inventive Principle:
Principle #25Self-service

2Measurement precision

If external oscilloscope measurements are used, then signal quality can be observed, but ease of operation deteriorates

Engineering Contradiction:
Improvesignal quality assessmentVSAvoidmeasurement convenience
Core Design Contradiction:
Measurement precisionVSEase of operation

Solution Approach 1:

The memory controller autonomously performs signal quality measurement by capturing its own output signal through the feedback path and sampling it internally. This self-service approach eliminates the need for external operators to use oscilloscopes, significantly improving ease of operation while maintaining measurement precision

Inventive Principle:
Principle #25Self-service

3Measurement precision

If feedback path with variable reference voltage is implemented, then signal quality measurement capability is improved, but device complexity increases

Engineering Contradiction:
Improvesignal quality measurementVSAvoidcircuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The feedback path is designed to serve multiple functions: it captures the output signal, provides feedback to the memory controller, and enables signal quality measurement. By making the feedback path multi-functional, the patent reduces the need for separate dedicated measurement circuits, thereby improving measurement precision without proportionally increasing device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10902896B2Memory circuit and method thereof
Publication Date: 2021.01.26 REALTEK SEMICON CORP
  • US10902896B2 patent drawing
  • US10902896B2 patent drawing
  • US10902896B2 patent drawing

AI summary

The present disclosure is related to a memory circuit. The memory includes a memory controller and a memory interface coupled between the memory controller and a memory device. The memory controller is configured to generate an output signal that is transmitted to the memory device. The memory interface includes a feedback path configured to receive the output signal and generates a feedback signal in response to the output signal and a variable reference voltage. The memory controller further includes a data register so as to sample the feedback signal in response to a clock signal having a phase with an adjustable shift.