Memory Fence Register for Multi-Level Transaction Completion
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Solution Overview
Problem
In complex System on Chip (SoC) designs with multiple cores, synchronizing memory access and tracking transaction status across multiple requesters is challenging due to the complexity and high performance requirements, leading to difficulties in ensuring that memory requests are completed and ordered correctly.
Innovation Solution
A status reporting mechanism is implemented using a specialized fence register and memory fence instruction that tracks transactions initiated by each master, ensuring completion and ordering of memory transactions, with a fence register indicating idle status and a memory fence instruction stalling the pipeline until all outstanding traffic is completed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a hierarchical and partitioned chip interconnect is used to meet performance requirements, then bandwidth and latency requirements are satisfied, but synchronization of accesses to shared resources becomes difficult
Solution Approach 1:
The patent implements a feedback mechanism where the memory system provides status information back to requesters through a fence register. The fence register is updated based on the completion status of memory transactions, allowing requesters to poll and determine when their transactions have completed. This feedback loop enables synchronization without requiring complex coordination protocols in the interconnect fabric.
Solution Approach 2:
Each requester is empowered to independently track its own transaction status by polling the fence register. The memory system automatically updates the fence register with completion status information. This self-service approach eliminates the need for centralized arbitration or complex interconnect-based synchronization mechanisms, reducing overall system complexity while maintaining synchronization capability.
2Productivity
If multiple requesters access shared memory resources simultaneously, then system throughput is improved, but tracking and ensuring completion of individual transactions becomes difficult
Solution Approach 1:
The fence register is segmented into multiple status bits, with each bit corresponding to a specific requester or transaction type. This segmentation allows the memory system to track the completion status of multiple concurrent transactions independently. Each requester can monitor its specific transaction status by checking the relevant bit in the fence register, preventing loss of transaction status information even when multiple requesters are active simultaneously.
3Speed
If memory transactions are processed in parallel across multiple cores, then processing speed is increased, but maintaining correct ordering of transactions becomes challenging
Solution Approach 1:
The fence register provides feedback on the completion status of transactions in a manner that preserves ordering information. By polling the fence register, requesters can determine when transactions have completed in the correct order. The memory system updates the fence register to reflect the actual completion status, providing feedback that enables software to maintain ordering requirements even when transactions are processed in parallel, thus preserving stability of transaction composition.
Data Source
AI summary
A system has memory resources accessible by a central processing unit (CPU). One or more transaction requests are initiated by the CPU for access to one or more of the memory resources. Initiation of transaction requests is ceased for a period of time. The memory resources are monitored to determine when all of the transaction requests initiated by the CPU have been completed. An idle signal accessible by the CPU is provided that is asserted when all of the transaction requests initiated by the CPU have been completed.