Semiconductor Memory Flag Generating Circuit for Power and Speed Optimization
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving high operational speeds with low power consumption, particularly in mobile devices, where rapid data processing with minimal resources is required.
Innovation Solution
A semiconductor memory device is designed with a memory circuit, a flag-generating circuit, and an output circuit that includes a preliminary flag-generating circuit to produce flag signals such as duplicate data flags and data bus inversion flags, enabling efficient data output through global input/output lines, optimizing data transmission by inverting or not inverting data based on logic levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data is transmitted through global input/output lines in conventional manner, then data transmission is performed, but power consumption increases and transmission speed is limited
Solution Approach 1:
The flag-generating circuit performs preliminary analysis of data patterns before actual data transmission. By generating duplicate data flags and data bus inversion flags in advance based on predicted data patterns, the system prepares optimization information that enables power-efficient and high-speed data transmission without compromising the actual data processing speed
Solution Approach 2:
Flag signals serve as intermediary elements between the memory circuit and output circuit. These flags (duplicate data flags and data bus inversion flags) carry optimization information that mediates the transmission process, enabling the output circuit to adjust its operation for power efficiency and speed without directly processing the actual data content
2Productivity
If flag signals are generated for each bit line, then data transmission optimization is achieved, but device complexity increases
Solution Approach 1:
The flag-generating circuit performs multiple functions using a unified structure. It simultaneously generates both duplicate data flags and data bus inversion flags, and can adapt to different data patterns (all same logic level, different logic levels, inverted patterns) without requiring separate dedicated circuits for each function, thereby achieving high transmission efficiency without proportional increase in complexity
Data Source
AI summary
A semiconductor memory device may include a memory circuit including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines, and configured to output data from the memory cell coupled to each of the bit lines through a global input/output line; a flag-generating circuit configured to generate a flag signal received with respect to the bit lines. The flag signal may include at least one of a duplicate data flag signal and a data bus inversion flag signal based on number of data having a specific logic level among the data in the memory cell for each of the bit lines that may be provided through the global input/output line in a read operation; and an output circuit configured to output the data based on at least one of the duplicate data flag signal and the data bus is inversion flag signal.