Memory Error Correction Flip-Bit Routing for Lower Access Latency
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Solution Overview
Problem
Error correction in memory devices introduces significant latency due to indirect routing of bits, where data bits must wait for error-corrected flip bits to be propagated through the system, leading to delays in data access times.
Innovation Solution
Transmitting error-corrected flip bits directly to the flip decision component on a dedicated line, bypassing the need for data bits to wait for error correction, allowing data to be transmitted without delay, and using a flip decision component to determine inversion based on error-corrected flip bits and data bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction is performed by propagating error-corrected flip bits through indirect routing, then reliability is improved, but data access time increases due to propagation delays
Solution Approach 1:
The patent segments the error correction process into two independent parts: (1) error correction of flip bits at the flip bit error correction component, and (2) error correction of data bits at data bit error correction components. This segmentation allows data bits to be error corrected independently without waiting for flip bit correction to complete, thereby reducing data access time while maintaining reliability.
Solution Approach 2:
The patent implements preliminary action by having the flip bit error correction component correct flip bits in advance and make them available before data bits need to be error corrected. The data bit error correction components can then proceed with their error correction using the already-corrected flip bits, eliminating the propagation delay that would otherwise occur.
2Measurement precision
If data bits wait for error-corrected flip bits to be propagated, then error correction accuracy is improved, but productivity decreases due to delays
Solution Approach 1:
The patent divides the error correction functionality into separate components: a flip bit error correction component dedicated to correcting flip bits, and data bit error correction components for correcting data bits. This segmentation allows each component to operate independently and simultaneously, ensuring error correction accuracy is maintained while eliminating waiting delays that reduce productivity.
Solution Approach 2:
The patent introduces an intermediary mechanism where error correction information from the flip bit error correction component is made available to data bit error correction components without requiring data bits to wait for the complete propagation process. This intermediary information flow enables parallel error correction operations, maintaining accuracy while improving data access speed.
3Reliability
If indirect routing is used for error correction propagation, then system reliability is improved through comprehensive error checking, but device complexity increases due to propagation paths
Solution Approach 1:
The patent segments the error correction system into distinct functional blocks with dedicated error correction components for flip bits and data bits. This segmentation simplifies the routing structure by eliminating the need for complex indirect propagation paths, as each component has direct access to the error correction information it needs through the segmented architecture.
Solution Approach 2:
The patent changes the dimensional approach to error correction by transitioning from a sequential, multi-stage propagation path to a parallel, simultaneous error correction process. Data bit error correction components operate in parallel with flip bit error correction, accessing error correction information simultaneously rather than through sequential propagation, thereby reducing routing complexity.
Data Source
AI summary
Methods, systems, and devices for operating a memory device are described. An error correction bit flipping scheme may include methods, systems, and devices for performing error correction of one or more bits (e.g., a flip bit) and for efficiently communicating error correction information. The data bits and the flip bit (e.g., an error corrected flip bit) may be directly transmitted (e.g., to a flip decision component). The flip bit may be transmitted to the flip decision component over a dedicated and/or unidirectional line that is different from one or more other lines that carry data bits (e.g., to the flip decision component).