Semiconductor Memory Layout With Floated Active Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices become more highly integrated, they face challenges in maintaining reliability and electrical performance due to reduced size and design rules, which impact operating characteristics.
Innovation Solution
The semiconductor memory devices feature active regions that are floated from the substrate, with bit lines acting as wirings, and apply different well biases to the cell array and peripheral circuit regions, enhancing transistor switching functions and overall electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor devices are highly integrated to increase operating speed and reduce power consumption, then productivity and energy efficiency are improved, but reliability deteriorates due to reduced size and design rules
Solution Approach 1:
The device is divided into cell array region and peripheral circuit region with distinct active region configurations. The cell array uses conventional substrate-connected active regions for high-speed operation, while the peripheral circuit uses floated active regions for improved reliability and reduced leakage current, allowing each segment to be optimized independently
Solution Approach 2:
Different regions of the semiconductor device are given different structural qualities: the cell array region maintains traditional substrate-connected active regions for speed, while the peripheral circuit region employs floated active regions isolated by device isolation layer and insulating layer for reduced leakage and improved reliability, creating local optimization without compromising overall integration
2Productivity
If the size of MOS field effect transistor is reduced to achieve high integration, then productivity is improved, but electrical performance deteriorates due to scaling limitations
Solution Approach 1:
The active regions are extended vertically by floating them above the substrate using device isolation layer and insulating layer, creating a three-dimensional structure that increases effective channel area and electrical performance without increasing planar footprint, thus maintaining high integration density while improving electrical characteristics
3Reliability
If active regions are floated from the substrate using device isolation layer and insulating layer, then reliability is improved by reducing leakage current, but device complexity increases
Solution Approach 1:
The device isolation layer and insulating layer serve multiple functions simultaneously: they electrically isolate the active regions from the substrate to reduce leakage current, provides mechanical support for the floated active regions, enable different biasing conditions for peripheral circuits, and maintain planarization for subsequent processing steps, reducing the need for additional specialized structures
Data Source
AI summary
A method of manufacturing a semiconductor memory device includes forming a first peripheral active region and a second peripheral active region spaced apart from each other on a first substrate; forming a bit line on the first and second peripheral active regions; forming an insulating layer on the bit line; bonding a second substrate on the insulating layer; removing the first substrate to expose one surface of each of the first and second peripheral active regions; and forming a gate electrode on the exposed one surface of each of the first and second peripheral active regions.