Semiconductor Memory Floating Access Method
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Solution Overview
Problem
Conventional semiconductor memory devices with variable resistance memory cells face challenges in efficiently distinguishing selected memory cells from unselected ones, leading to high current consumption and limited scalability, which hinders the utilization of three-dimensional structures for mass storage applications.
Innovation Solution
The semiconductor memory device employs a floating access method where unselected memory cells are brought into a self-aligned bias state, reducing current consumption by dividing the set voltage among multiple unselected cells and minimizing capacitive coupling effects, thereby ensuring reliable write operations without increasing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bias is applied to unselected memory cells to distinguish them from selected memory cells, then the reliability of memory cell operation is improved, but the current consumption increases
Solution Approach 1:
The unselected memory cells are left in a floating state, allowing them to self-align to an intermediate potential through capacitive coupling with selected lines. This eliminates the need for active bias application circuits, reducing current consumption while maintaining reliable operation through the natural voltage division effect
Solution Approach 2:
The patent changes the voltage state of unselected memory cells from an actively biased state to a floating state that naturally settles at an intermediate potential. This parameter change reduces power consumption while maintaining the voltage margin needed for reliable operation, as the floating cells automatically adjust to safe voltage levels through capacitive coupling
2Quantity of substance
If the cell array size is increased to utilize three-dimensional structure for mass storage, then the storage capacity is improved, but the current consumption per cell increases due to bias requirements
Solution Approach 1:
The patent segments the voltage application strategy by applying full voltage only to selected memory cells while leaving unselected cells in a floating state. This segmentation allows the cell array to be scaled to large three-dimensional structures for mass storage without proportionally increasing current consumption, as only a small fraction of cells (the selected ones) require active voltage application at any given time
Solution Approach 2:
The patent enables three-dimensional stacking of memory cell arrays, utilizing the vertical dimension to increase storage capacity. By combining this with the floating access method, the system achieves high-density storage without the current consumption scaling that would otherwise result from biasing all cells in the expanded array, effectively decoupling capacity scaling from power consumption scaling
3Reliability
If optimal bias condition is applied to selected memory cell for access, then the write operation reliability is improved, but the voltage distribution to unselected cells causes current consumption increase
Solution Approach 1:
The patent extracts the bias application requirement specifically to selected memory cells only, removing the need to apply bias to unselected cells. By leaving unselected cells in a floating state, the system eliminates energy loss in these cells while maintaining optimal voltage conditions for selected cells, achieving write operation reliability without the associated energy penalty
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and prevents data disturb, allowing for efficient and reliable write operations while maintaining a sufficient disturb margin, thus enabling the effective use of three-dimensional structures for large-capacity memory applications.
Implementation Method 1
minimizing capacitive coupling effects
Data Source
Figure 1~2
Figure 3(A)~3(B)
Figure 4~5
AI summary
A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state.