Memory Plane Floorplan Layout for Direct Peripheral Communication
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Solution Overview
Problem
Existing semiconductor memory devices face increased cost and reduced memory density due to peripheral metal routing around obstacles, which separates necessary circuitry components, necessitating inefficient communication and larger chip sizes.
Innovation Solution
A novel circuitry arrangement in the CMOS layer of a memory device where planes are oriented with different major dimensions, allowing direct communication between common and non-common peripheral circuitry areas without additional metal contacts, reducing wiring blockage and optimizing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If peripheral metal routing is used around obstacles to establish electrical communication between circuitry components, then electrical communication is established, but chip size increases and manufacturing cost increases
Solution Approach 1:
The patent transitions from two-dimensional peripheral routing around obstacles to three-dimensional vertical stacking, where memory planes are stacked above each other with shared peripheral circuitry areas in the vertical dimension, eliminating the need for extended peripheral metal routing
Solution Approach 2:
The patent merges peripheral circuitry areas across multiple memory planes by positioning them in vertical alignment, allowing shared circuitry to serve multiple planes simultaneously and eliminating redundant routing for each individual plane
2Reliability
If peripheral metal routing is used around obstacles to establish electrical communication between circuitry components, then electrical communication is established, but manufacturing cost increases
Solution Approach 1:
The patent uses vertical stacking to eliminate complex peripheral routing, reducing the number of metal layers and routing complexity, which directly lowers manufacturing cost
Solution Approach 2:
By merging peripheral circuitry areas vertically across multiple planes, the patent reduces the total amount of metal routing required, simplifying the manufacturing process and reducing costs
3Reliability
If circuitry components are separated by obstacles requiring peripheral metal routing, then component isolation is achieved, but memory density decreases
Solution Approach 1:
The patent resolves the conflict between isolation and density by moving isolation to the vertical dimension through stacked planes, allowing horizontal space to be maximized for memory cells while maintaining isolation through layer separation
Solution Approach 2:
The patent nests multiple memory planes vertically within a compact footprint, with each plane containing memory blocks and peripheral circuitry areas positioned to share resources, effectively increasing memory density without compromising isolation
Data Source
AI summary
The memory device includes a die with a first set of planes and a second set of planes. The planes are rectangular in shape with a major dimension and a minor dimension. The die includes a CMOS layer with at least one common peripheral circuitry area, and each of the planes includes a non-common peripheral circuitry area in the CMOS layer. Each plane of the first set of planes is oriented such that its major dimension extends in a first direction, and each plane of the second set of planes is oriented such that its major dimension extends in a second direction that is different than the first direction such that the non-common peripheral circuitry area of each plane is immediately adjacent the at least one common peripheral circuitry area in the CMOS layer.