Memory Folding Circuits for On-Chip FFT/CZT Transforms
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Solution Overview
Problem
Existing FFT and CZT computations require accessing large amounts of off-chip high-bandwidth memory (HBM), which is costly and complicates the system, especially for high data rates and long integration times, leading to slow processing and increased costs.
Innovation Solution
A processing circuit on a single chip performs frequency-based transforms using on-chip memory for in-place block processing, where data is stored and processed within the same memory locations, allowing for rotated or unrotated access as needed, eliminating the need for off-chip HBM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If off-chip high-bandwidth memory (HBM) is used to handle large data volumes for FFT/CZT computations, then data storage capacity is improved, but system cost and complexity increase
Solution Approach 1:
The patent implements a nested memory structure where multiple memory banks are organized hierarchically within the FPGA device. Memory banks are grouped into memory bank groups, with each bank containing multiple memory elements. This nested organization allows efficient data storage and access patterns that eliminate the need for external HBM while maintaining required data capacity for large FFT/CZT computations.
Solution Approach 2:
The patent transforms the memory access problem from a two-dimensional (off-chip HBM) solution to a multi-dimensional on-chip memory architecture. By organizing memory into banks, bank groups, and individual elements with specific address mapping relationships, the system creates additional dimensional layers for data storage and retrieval, enabling sufficient capacity within the FPGA without external memory.
2Quantity of substance
If off-chip HBM is used for storing large data volumes, then data capacity is improved, but processing speed decreases
Solution Approach 1:
The patent merges multiple memory banks into memory bank groups that can be accessed in parallel. By combining the capabilities of multiple memory elements and banks, the system achieves both high data capacity and fast access speeds, as parallel access to multiple banks eliminates the bandwidth limitations of sequential off-chip memory access.
Solution Approach 2:
The patent implements preliminary organization of data into specific memory bank groups and banks based on the computation requirements. Data is pre-positioned in optimal memory locations before processing begins, allowing immediate parallel access during FFT/CZT computations without the latency associated with dynamic memory allocation or off-chip memory access.
3Ease of manufacture
If data is stored in on-chip memory with columnar organization, then memory utilization is improved, but access pattern complexity increases
Solution Approach 1:
The patent implements dynamic memory addressing and access control that adapts to different computation stages. The memory controller dynamically selects which memory banks to access and in what order, optimizing access patterns for each specific FFT/CZT operation while maintaining the efficient columnar storage organization. This dynamic approach handles the apparent complexity through automated control logic.
4Device complexity
If on-chip memory is used for in-place processing, then system cost is reduced, but memory access requirements increase
Solution Approach 1:
The patent segments the memory system into multiple independent memory banks organized in bank groups, allowing parallel access operations. This segmentation enables the memory subsystem to handle increased access requirements by distributing memory operations across multiple banks simultaneously, maintaining high efficiency while using only on-chip memory resources.
Data Source
AI summary
A processing circuit for creating a frequency-based output data from sampled streaming analog input data that is provided in K-deep input data blocks where K is a number of samples per clock cycle. The system includes: a memory unit on the single chip to store data including the sampled streaming analog input data; a processing engine on the single chip that receives the incoming streaming data as a series of K-deep input data blocks and performs a portion a frequency transform on the incoming streaming data to produce processed data. The system also includes a memory controller that causes the processed data to initially be stored by column in the memory unit. The memory controller reads data in the memory out in a rotated manner, provides it to the processing engine so that processing engine creates new processed data and writes the new processed data back into the memory.