Memory Device Footswitch and Headswitch Leakage Reduction

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Solution Overview

Problem

Existing memory devices face significant leakage current issues during sleep mode due to reduced threshold voltage, leading to increased power consumption and battery drain, particularly in portable electronic devices like mobile phones and PDAs, which complicates the implementation of headswitch or footswitch circuitry for power rail collapse.

Innovation Solution

A memory device design that includes a memory core array with bitlines, peripheral logic isolated by a footswitch from ground voltage, and a headswitch isolating the precharge current path from the supply voltage to the bitlines, effectively reducing leakage current during sleep mode by disconnecting power and ground supplies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the threshold voltage of CMOS devices is reduced to avoid increases in propagation delay, then the operating speed is improved, but the stand-by leakage current increases exponentially

Engineering Contradiction:

Improvepropagation delayVSAvoidstand-by leakage current

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The power supply network is segmented into multiple regions, each with its own headswitch and footswitch. This allows different threshold voltage regions (LVT and HVT) to be independently controlled, enabling fast switching in LVT regions while maintaining low leakage in HVT regions during stand-by mode

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different threshold voltage characteristics are applied to different parts of the circuit. LVT gates are used in regions requiring fast switching, while HVT gates are used in regions where low leakage is critical. The headswitches and footswitches are strategically placed to control power delivery to these different regions with different quality requirements

Inventive Principle:

Principle #3Local quality

2Loss of energy

If headswitches or footswitches are implemented on a global basis to collapse the power rail for a large array of logic cells, then the leakage current is reduced, but the device complexity and area overhead increase significantly

Engineering Contradiction:

Improveleakage currentVSAvoidcomplexity of headswitch/footswitch implementation

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The headswitches and footswitches are designed to be universal building blocks that can be replicated and applied to multiple logic cells. The same basic switch structure serves both LVT and HVT regions, reducing the need for custom design tools and special routing for each cell type

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

Instead of implementing headswitches and footswitches in every single logic cell, the patent applies them selectively to regions where leakage reduction is most beneficial. This partial application reduces the overall complexity and area overhead while still achieving significant leakage current reduction

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS9916904B2Reducing leakage current in a memory device

Publication Date: 2018.03.13 QUALCOMM INC

AI summary

Memory devices and methods of reducing leakage current therein are disclosed. The memory device includes a memory core array including a plurality of bitlines, and peripheral logic configured to interface with the memory core array. The memory device further includes a footswitch configured to isolate the peripheral logic from a ground voltage, and a headswitch configured to isolate a precharge current path from the plurality of bit lines of the memory core array. Leakage current within the memory device may be reduced via the isolation provided by the footswitch and the headswitch.