Memory Device Forming by Interconnect-Resistance Sequencing
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Solution Overview
Problem
Existing memory devices using variable resistance elements face challenges in reliably changing the current-voltage characteristics of switching elements during the forming process, leading to potential failures and inconsistencies in performance.
Innovation Solution
A method is introduced where memory cells are selected based on their interconnect resistance or other factors to perform the forming process sequentially, ensuring that cells with higher resistance are addressed first, thereby optimizing the application of voltage and reducing the risk of insulation breakdown and forming failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the forming process is performed on all memory cells simultaneously or in random order, then the process is simple and fast, but the reliability of switching elements decreases due to variations in potential difference across cells
Solution Approach 1:
The forming process is segmented into multiple sequential steps, where memory cells are divided into groups based on their interconnect resistance characteristics. Each group is processed separately with optimized voltage conditions, rather than applying uniform voltage to all cells simultaneously. This segmentation allows tailored forming conditions for different cell types, improving reliability while managing complexity through systematic grouping.
Solution Approach 2:
The invention changes the voltage parameter dynamically based on cell characteristics. Different voltage magnitudes are applied to different groups of memory cells depending on their interconnect resistance. High-resistance cells receive higher voltages while low-resistance cells receive lower voltages, optimizing the forming process for each group and preventing insulation breakdown.
2Productivity
If high voltage is applied to all memory cells during forming, then the forming process is efficient, but insulation breakdown occurs in cells with low interconnect resistance
Solution Approach 1:
The forming process applies local quality by tailoring voltage magnitude to specific cell groups based on their interconnect resistance characteristics. Instead of uniform high voltage, each group receives appropriately sized voltage pulses - higher for high-resistance cells, lower for low-resistance cells. This localized optimization maintains forming efficiency for each cell type while preventing harmful insulation breakdown in sensitive cells.
Solution Approach 2:
The invention uses partial action by applying different voltage levels to different cell groups rather than excessive uniform high voltage to all cells. This partial differentiation of voltage application ensures sufficient forming action for high-resistance cells while avoiding excessive voltage that would cause breakdown in low-resistance cells, thus maintaining overall process efficiency without harmful effects.
3Reliability
If low voltage is applied during forming, then insulation breakdown is prevented, but forming failures increase due to insufficient voltage for high-resistance cells
Solution Approach 1:
The invention implements preliminary action by measuring or estimating interconnect resistance before the forming process and using this information to pre-categorize cells into voltage groups. This preliminary classification enables optimized voltage application without real-time feedback during forming, achieving high forming success rates while keeping control complexity manageable through advance preparation.
Solution Approach 2:
The voltage parameter is changed based on cell characteristics - higher voltages are applied to cells with higher interconnect resistance while lower voltages are applied to cells with lower resistance. This parameter differentiation ensures sufficient voltage for forming in high-resistance cells without causing breakdown in low-resistance cells, improving overall forming success rate while managing control complexity through systematic voltage levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of switching elements by minimizing variations in potential difference across cells, reducing the likelihood of forming failures, and maintaining consistent performance across the memory device.
Implementation Method 1
changing a current-voltage characteristic of the switching element SW from an initial state
Data Source
AI summary
According to one embodiment, a memory device includes first interconnects in a first direction, second interconnects in a second direction intersecting the first direction, and memory cells. Each of the memory cells is associated with a set of one of the first interconnects and one of the second interconnects between the first interconnects and the second interconnects and includes a variable resistance element and a switching element which are coupled in series. A forming method of the memory device includes: selecting a memory cell having a highest interconnect resistance from memory cells on which a forming process has not been performed; performing a forming process on a switching element in the selected memory cell; and repeating the selecting and the performing on the memory cells.