Memory Free List Allocation for Bounded DRAM Tail Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing DRAM latency is high due to factors like bitline precharge, row activation, column access, and refresh operations, which affect overall system performance, and conventional striding techniques increase power consumption and may result in random distribution of memory accesses leading to high tail latency.
Innovation Solution
Implementing memory free list latency bounding techniques by maintaining separate free lists for each memory device, distributing data chunks across multiple devices based on device availability and recency of selection, optimizing access patterns to reduce average and tail latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional striding techniques are used to distribute memory accesses across multiple memory devices, then memory access distribution is achieved, but power consumption increases and tail latency becomes high due to random distribution patterns
Solution Approach 1:
The patent maintains free lists in advance for each memory device, pre-organizing free locations before they are needed. This preliminary organization allows the memory controller to efficiently allocate data chunks without random access patterns, reducing both power consumption and tail latency while maintaining good distribution across memory devices.
2Device complexity
If data is stored sequentially in memory devices, then simplicity of allocation is maintained, but latency increases due to lack of distribution across multiple devices
Solution Approach 1:
The patent segments the free location space into separate free lists for each memory device. This segmentation allows the system to maintain allocation simplicity within each device while achieving distribution across multiple devices, thereby reducing latency without significantly increasing complexity.
Solution Approach 2:
The patent introduces a new dimension of organization by creating separate free lists for each memory device rather than using a single sequential allocation approach. This dimensional change enables parallel access patterns across multiple devices, reducing latency while keeping the allocation mechanism relatively simple.
3Loss of time
If free lists are maintained for each memory device, then latency is reduced through better distribution, but device complexity increases due to additional data structures
Solution Approach 1:
The free lists are maintained to automatically track free locations in each memory device, enabling the memory controller to self-organize data allocation without complex external management. This self-service approach reduces latency through better distribution while keeping the complexity manageable by leveraging the natural structure of free list data structures.
Data Source
AI summary
Memory free list latency bounding techniques may optimize the performance of parallel storage devices. In one example, a memory controller includes one or more registers that include pointers to free lists that include addresses of free locations in the memory devices. In various example, each free list corresponds to a memory device, memory module, or pseudo channel. The memory controller receives data to store in memory. The memory controller splits the data into data chunks, where a data chunk has a size that is greater than a memory access size. The memory controller then determines which free lists include addresses to free locations and selects one or more memory devices to store the data chunks based on the free lists. In one example, at least one of the memory devices is selected to store data chunks based on how recently the memory device was selected.