Memory Device Frequency-Based Storage Segmentation

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Solution Overview

Problem

Neuromorphic computer systems face reliability and efficiency issues due to memory devices that do not consider data frequency of use during programming, leading to suboptimal storage and retrieval operations.

Innovation Solution

A memory device with multiple memory areas, including SLC and MLC regions, and a controller that dynamically stores data based on frequency of use and importance, using different read operations for each area to optimize storage and retrieval efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is stored in a single memory area without considering frequency of use, then device complexity is reduced, but data reliability and operating efficiency are degraded

Engineering Contradiction:
Improvedata reliabilityVSAvoidmemory structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory device is divided into multiple memory areas (first memory area and second memory area) with different characteristics. The controller segments data storage by frequency of use, placing frequently accessed data in one area and less frequently accessed data in another, thereby improving reliability without requiring a completely new memory architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The memory allocation is dynamic rather than static. The controller dynamically determines which memory area to use based on the frequency of use of data being stored. This dynamic adaptation allows the system to optimize for reliability when needed while maintaining manageable complexity through software-controlled allocation.

Inventive Principle:
Principle #15Dynamics

2Speed

If frequently used data is stored in high-speed memory area, then data access speed is improved, but memory space utilization is reduced

Engineering Contradiction:
Improvedata access speedVSAvoidmemory space utilization
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

Different memory areas are assigned different qualities or characteristics. The first memory area is optimized for speed to handle frequently accessed data, while the second memory area is optimized for capacity to store less frequently accessed data. This local differentiation allows the system to achieve high speed for critical operations without sacrificing overall storage capacity.

Inventive Principle:
Principle #3Local quality

3Quantity of substance

If data is stored in memory area optimized for capacity, then storage efficiency is improved, but data retrieval speed is reduced

Engineering Contradiction:
Improvestorage capacityVSAvoiddata retrieval speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The storage system is segmented into multiple areas with different performance characteristics. By segmenting the memory into first and second areas, the system can place capacity-optimized storage for less frequently accessed data in the second memory area, accepting slower retrieval speed only when necessary, while maintaining overall system efficiency.

Inventive Principle:
Principle #1Segmentation

4Productivity

If memory device uses multiple read operations for different memory areas, then operating efficiency is improved, but device complexity increases

Engineering Contradiction:
Improveoperating efficiencyVSAvoidcontrol operation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The controller is designed with multi-functionality to handle different read operations for different memory areas. A single controller component performs multiple functions: managing first read operations for the first memory area and second read operations for the second memory area. This universal approach improves operating efficiency without proportionally increasing overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11237983B2Memory device, method of operating memory device, and computer system including memory device
Publication Date: 2022.02.01 SAMSUNG ELECTRONICS CO LTD
  • US11237983B2 patent drawing
  • US11237983B2 patent drawing
  • US11237983B2 patent drawing

AI summary

A memory device includes; a memory area including a first memory area including first memory cells storing N-bit data and a second memory area including second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.