Memory Clock Frequency Control by Transaction Queue Occupancy
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Solution Overview
Problem
Existing heuristics for controlling clock frequencies in integrated circuit devices of electronic devices are flawed, leading to inefficient power consumption due to inaccurate detection of memory access patterns, resulting in either unnecessary increases or decreases in clock frequency.
Innovation Solution
Implementing heuristics that utilize transaction queue occupancy to dynamically adjust clock frequencies based on transaction queue thresholds, including monitoring the occupied portion of the transaction queue and adjusting the clock frequency accordingly to prevent stalls or waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock frequency is increased to improve memory access performance, then productivity is improved, but use of energy increases
Solution Approach 1:
The patent applies dynamics by making the clock frequency adjustable rather than fixed. The memory controller dynamically changes the clock frequency based on real-time transaction queue occupancy levels, transitioning between high frequency (when queue is full, indicating high demand) and low frequency (when queue is empty, indicating low demand). This dynamic adjustment allows the system to optimize both performance and power consumption according to actual workload conditions.
Solution Approach 2:
The patent implements feedback by using transaction queue occupancy as a control signal. The memory controller continuously monitors the transaction queue status and uses this feedback information to adjust the clock frequency. When the queue occupancy exceeds a threshold, the controller increases frequency to improve performance; when occupancy drops below the threshold, the controller decreases frequency to save power. This closed-loop feedback mechanism ensures optimal balance between productivity and energy consumption.
2Use of energy by moving object
If clock frequency is decreased to reduce power consumption, then use of energy is improved, but productivity deteriorates
Solution Approach 1:
The system dynamically adjusts clock frequency based on actual memory access demands reflected in transaction queue occupancy. Rather than maintaining a low frequency that would permanently reduce performance, the system can quickly increase frequency when demand arises. This dynamic capability allows the system to minimize power consumption during low-demand periods while ensuring high performance is available when needed, thus resolving the contradiction between energy efficiency and productivity.
Solution Approach 2:
The patent applies preliminary action by proactively adjusting the clock frequency before performance degradation or excessive power consumption occurs. The memory controller monitors transaction queue occupancy in advance and anticipates future performance needs. When occupancy approaches thresholds, the system preemptively adjusts frequency to prevent stalls or wasted power, rather than reacting after problems have manifested. This proactive approach maintains optimal balance between power consumption and performance.
3Device complexity
If existing heuristics are used to control clock frequency, then device complexity is reduced, but measurement precision of memory access patterns deteriorates
Solution Approach 1:
The patent applies self-service by using the transaction queue's own occupancy status as the measurement mechanism. Instead of requiring complex external monitoring systems or sophisticated sensors to detect memory access patterns, the system leverages the queue's inherent state information. The transaction queue occupancy level directly reflects memory access demand, providing a simple yet accurate measurement that is already part of the memory controller's operational state. This self-service approach maintains simplicity while achieving high measurement precision.
Data Source
AI summary
Techniques and apparatuses are described that use transaction queue lengths to alter a clock frequency that controls access to a memory of an electronic device. Techniques include detecting that a transaction queue threshold has been violated, initiating a counter to measure a time duration, determining that the transaction queue threshold continues to be violated for the time duration and, in response, altering the clock frequency that controls access to the memory of the electronic device.