Memory Device Frequency-Based Data Storage Segmentation
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Solution Overview
Problem
Neuromorphic computer systems and memory devices face inefficiencies and reliability issues due to methods of data storage and access that do not consider the frequency of use, leading to suboptimal performance and resource management.
Innovation Solution
Implementing a memory device with distinct memory areas and read operations tailored to data frequency of use, where data is stored and read based on its frequency of use, using different access operations and memory cell types, such as SLC, MLC, TLC, and QLC, to optimize storage and retrieval efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in memory cells without considering frequency of use, then storage space is utilized, but data reliability and operating efficiency are degraded
Solution Approach 1:
The memory device is divided into multiple memory areas (first memory area with N-bit memory cells, second memory area with M-bit memory cells where M>N) to store data with different frequencies of use. Frequently accessed data is stored in the first memory area while less frequently accessed data is stored in the second memory area, thereby improving both reliability and operating efficiency simultaneously.
2Reliability
If data is distributed across multiple memory areas using different access operations, then data reliability is improved, but device complexity increases
Solution Approach 1:
Different memory areas are assigned different data access operations based on the frequency of use of the data they store. The first memory area uses a first data access operation optimized for frequently accessed data, while the second memory area uses a second data access operation for less frequently accessed data. This local differentiation improves reliability without requiring complete system redesign.
Solution Approach 2:
The memory device incorporates a controller that can selectively manage data across multiple memory areas with different access operations. This universal controller handles both first and second data access operations, allowing the device to adapt to different data access patterns while maintaining a unified management structure, thereby limiting the increase in device complexity.
3Speed
If different read operations are used for different memory areas, then data access speed is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent employs different read operations (first read operation and second read operation) for different memory areas, where the operations differ in parameters such as read voltage, sense amplifier activation, or timing sequences. This allows optimization of data access speed for different data types while using standard memory cell structures that can be manufactured with existing processes, thereby limiting the increase in manufacturing complexity.
Data Source
AI summary
A memory device comprises a memory cell region including a first metal pad, and a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, wherein the memory cell region includes a first memory area having first memory cells storing N-bit data and a second memory area having second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and the peripheral circuit region includes a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.