Memory Front End Precharge for Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current digital memory architectures consume excessive power due to the need to precharge all bit lines before each access cycle, which is inefficient, especially when only a subset of bit lines are accessed, and result in increased latency and power consumption, particularly in mobile applications where low power and random access are crucial.
Innovation Solution
The solution involves selectively precharging only the subset of bit lines required for an access operation, allowing the precharge and access cycles to occur simultaneously, and enabling only necessary sense amplifiers to conserve power and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all bit lines are precharged before each access cycle, then reliable memory access is ensured, but power consumption increases significantly
Solution Approach 1:
The memory bank is divided into multiple sub-banks, each with its own set of bit lines. Only the sub-bank containing the target address is precharged, while other sub-banks remain in high-impedance state. This segmentation allows selective precharging of bit lines, reducing power consumption while maintaining access reliability.
Solution Approach 2:
Instead of precharging all bit lines in the bank, only the necessary portion (sub-bank) is precharged. The precharge operation is performed partially on the required subset of bit lines, avoiding the excessive action of precharging the entire bank and thereby reducing power consumption.
2Reliability
If all bit lines are precharged before each access cycle, then complete access readiness is achieved, but access latency increases
Solution Approach 1:
By segmenting the bank into sub-banks with independent precharge control, the precharge operation can be performed on only the necessary sub-bank. This reduces the overall precharge time required before access, thereby reducing access latency while ensuring the targeted sub-bank is fully ready.
Solution Approach 2:
The precharge operation is performed preliminarily on only the required sub-bank before the access cycle begins. This preliminary action ensures the necessary bit lines are ready in advance without delaying the access operation, as other sub-banks do not need to be precharged.
3Adaptability or versatility
If entire bank is precharged to access small number of bits, then complete access capability is provided, but power and temperature increase
Solution Approach 1:
The bank is segmented into sub-banks that can be independently precharged. When only a small number of bits need to be accessed, only the corresponding sub-bank is precharged, providing the necessary access capability without the excessive power consumption of precharging the entire bank.
Solution Approach 2:
Different regions (sub-banks) of the memory have different operational states. The accessed sub-bank is in a precharged ready state, while non-accessed sub-banks remain in high-impedance state. This local quality differentiation allows power-efficient operation tailored to the specific access pattern.
4Reliability
If all sense amplifiers are enabled for access, then complete data sensing capability is achieved, but power consumption increases
Solution Approach 1:
Sense amplifiers are grouped with their corresponding sub-banks. When a specific sub-bank is accessed, only the sense amplifiers associated with that sub-bank are enabled. This segmentation of sense amplifier control allows complete data sensing capability for the accessed region while avoiding the power consumption of enabling all sense amplifiers.
Data Source
AI summary
Methods, apparatuses and systems of operating digital memory where the digital memory device including a plurality of memory cells receives a command to perform an operation on a set of memory cells, where the set of memory cells contains fewer memory cells than the device as a whole and where the device performs the operation including selectively precharging on the front end of the operation, in response to the received command, only a set of bit lines associated with the set of memory cells.